Decimation of baseband DTV signals prior to channel equalization in digital television signal receivers

ABSTRACT

A radio receiver uses the same tuner for receiving a selected digital television (DTV) signal, irrespective of whether it is a quadrature-amplitude-modulation (QAM) or a vestigial sideband (VSB) signal. The final IF signal is digitized at a rate that is a multiple of both the symbol frequencies of the QAM and VSB signals, for synchrodyning to baseband. The carrier frequencies of the QAM and VSB final IF signals are regulated to be submultiples of the multiple of both the symbol frequencies of the QAM and VSB signals by applying automatic frequency and phase control (AFPC) signals developed in the digital circuitry to a local oscillator of the tuner. Baseband DTV signals obtained by synchrodyning the final IF signals have a sample rate higher than symbol rate to facilitate symbol synchronization. The baseband DTV signals are decimated to symbol rate before performing channel equalization to reduce the number of multipliers required in the channel equalization filter.

This is a continuation-in-part of U.S. patent application Ser. No.08/773,949 filed Dec. 26, 1996, now abandoned.

The invention relates to radio receivers having the capability ofreceiving digital television (DTV) signals such as digitalhigh-definition television (HDTV) signals, transmitted using quadratureamplitude modulation (QAM) of the principal carrier wave or transmittedusing vestigial sideband (VSB) amplitude modulation of the principalcarrier wave.

BACKGROUND OF THE INVENTION

A Digital Television Standard published Sep. 16, 1995 by the AdvancedTelevision Systems Committee (ATSC) specifies vestigial sideband (VSB)signals for transmitting digital television (DTV) signals in6-MHz-bandwidth television channels such as those currently used inover-the-air broadcasting of National Television System Committee (NTSC)analog television signals within the United States. The VSB DTV signalis designed so its spectrum is likely to interleave with the spectrum ofa co-channel interfering NTSC analog TV signal. This is done bypositioning the pilot carrier and the principal amplitude-modulationsideband frequencies of the DTV signal at odd multiples of one-quarterthe horizontal scan line rate of the NTSC analog TV signal that fallbetween the even multiples of one-quarter the horizontal scan line rateof the NTSC analog TV signal, at which even multiples most of the energyof the luminance and chrominance components of a co-channel interferingNTSC analog TV signal will fall. The video carrier of an NTSC analog TVsignal is offset 1.25 MHz from the lower limit frequency of thetelevision channel. The carrier of the DTV signal is offset from suchvideo carrier by 59.75 times the horizontal scan line rate of the NTSCanalog TV signal, to place the carrier of the DTV signal about 309,877.6Hz from the lower limit frequency of the television channel.Accordingly, the carrier of the DTV signal is about 2,690122.4 Hz fromthe middle frequency of the television channel. The exact symbol rate inthe Digital Television Standard is (684/286) times the 4.5 MHz soundcarrier offset from video carrier in an NTSC analog TV signal. Thenumber of symbols per horizontal scan line in an NTSC analog TV signalis 684, and 286 is the factor by which horizontal scan line rate in anNTSC analog TV signal is multiplied to obtain the 4.5 MHz sound carrieroffset from video carrier in an NTSC analog TV signal. The symbol rateis 10.762238 * 10⁶ symbols per second, which can be contained in a VSBsignal extending 5.381119 MHz from DTV signal carrier. That is, the VSBsignal can be limited to a band extending 5.690997 MHz from the lowerlimit frequency of the television channel.

The ATSC standard for digital HDTV signal terrestrial broadcasting inthe United States of America is capable of transmitting either of twohigh-definition television (HDTV) formats with 16:9 aspect ratio. OneHDTV format uses 1920 samples per scan line and 1080 active horizontalscan lines per 30 Hz frame with 2:1 field interlace. The other HDTVformat uses 1280 luminance samples per scan line and 720 progressivelyscanned scan lines of television image per 60 Hz frame. The ATSCstandard also accommodates the transmission of DTV formats other thanHDTV formats, such as the parallel transmission of four televisionsignals having normal definition in comparison to an NTSC analogtelevision signal.

DTV transmitted by vestigial-sideband (VSB) amplitude modulation (AM)for terrestrial broadcasting in the United States of America comprises asuccession of consecutive-in-time data fields each containing 313consecutive-in-time data segments. There are 832 symbols per datasegment. So, with the symbol rate being 10.76 MHz, each data segment isof 77.3 microseconds duration. Each segment of data begins with a linesynchronization code group of four symbols having successive values of+S, −S, −S and +S. The value +S is one level below the maximum positivedata excursion, and the value −S is one level above the maximum negativedata excursion. The initial line of each data field includes a fieldsynchronization code group that codes a training signal forchannel-equalization and multipath suppression procedures. The trainingsignal is a 511-sample pseudo-noise sequence (or “PN-sequence”) followedby three 63-sample PN sequences. The middle one of these 63-sample PNsequences is transmitted in accordance with a first logic convention inthe first line of each odd-numbered data field and in accordance with asecond logic convention in the first line of each even-numbered datafield, the first and second logic conventions being one's complementaryrespective to each other. The other two 63-sample PN sequences and the511-sample PN sequence are transmitted in accordance with the same logicconvention in all data fields.

The data within data lines are trellis coded using twelve interleavedtrellis codes, each a ⅔ rate trellis code with one uncoded bit. Theinterleaved trellis codes have been subjected to Reed-Solomon forwarderror-correction coding, which provides for correction of burst errorsarising from noise sources such as a nearby unshielded automobileignition system. The Reed-Solomon coding results are transmitted as8-level (3 bits/symbol) one-dimensional-constellation symbol coding forover-the-air transmission, which transmissions are made without symbolpreceding separate from the trellis coding procedure. The Reed-Solomoncoding results are transmitted as 16-level (4 bits/symbol)one-dimensional-constellation symbol coding for cablecast, whichtransmissions are made without trellis coding. The VSB signals havetheir natural carrier wave, which would vary in amplitude depending onthe percentage of modulation, suppressed.

The natural carrier wave is replaced by a pilot carrier wave of fixedamplitude, which amplitude corresponds to a prescribed percentage ofmodulation. This pilot carrier wave of fixed amplitude is generated byintroducing a direct component shift into the modulating voltage appliedto the balanced modulator generating the amplitude-modulation sidebandsthat are supplied to the filter supplying the VSB signal as itsresponse. If the eight levels of 3-bit symbol coding have normalizedvalues of −7, −5, −3, −1, +1, +3, +5 and +7 in the carrier modulatingsignal, the pilot carrier has a normalized vale of 1.25. The normalizedvalue of +S is +5, and the normalized value of −S is −5.

VSB signals using 8-level symbol coding will intially be used inover-the-air broadcasting within the United States, and VSB signalsusing 16-level symbol coding can be used in over-the-air narrowcastingsystems or in cable-casting systems. However, certain cable-casting islikely to be done using suppressed-carrier quadrature amplitudemodulation (QAM) signals instead, rather than using VSB signals. Thispresents television receiver designers with the challenge of designingreceivers that are capable of receiving either type of transmission andof automatically selecting suitable receiving apparatus for the type oftransmission currently being received.

It is assumed that the data format supplied for symbol encoding is thesame in transmitters for the VSB DTV signals and in transmitters for theQAM DTV signals. The VSB DTV signals modulate the amplitude of only onephase of the carrier at symbol rate of 10.76 * 10⁶ symbols per second toprovide a real signal unaccompanied by an imaginary signal, which realsignal fits within a 6 MHz band because of its VSB nature with carriernear edge of band. Accordingly, the QAM DTV signals, which modulate twoorthogonal phases of the carrier to provide a complex signal comprisinga real signal and an imaginary signal as components thereof, aredesigned to have a symbol rate of 5.38 * 10⁶ symbols per second, whichcomplex signal fits within a 6 MHz band because of its QAM nature withcarrier at middle of band.

Processing after symbol decoding is similar in receivers for the VSB DTVsignals and in receivers for the QAM DTV signals, assuming the dataformat supplied for symbol encoding is the same in transmitters for theVSB DTV signals and in transmitters for the QAM DTV signals. The datarecovered by symbol decoding are supplied as input signal to a datade-interleaver, and the de-interleaved data are supplied to aReed-Solomon decoder. Error-corrected data are supplied to a datade-randomizer which regenerates packets of data for a packet decoder.Selected packets are used to reproduce the audio portions of the DTVprogram, and other selected packets are used to reproduce the videoportions of the DTV program.

The zero-intermediate-frequency (ZIF) receivers, which performamplification and channel selection at baseband, that are used forreceiving QAM DTV signals are not well suited for receiving VSB DTVsignals. This is because of problems with securing adequateadjacent-channel rejection in a ZIF receiver when the carrier is not atthe center frequency of the channel. The tuners can be quite similar inreceivers for the VSB DTV signals and in receivers for the QAM DTVsignals if the receivers are of superheterodyne types, however. Thedifferences in the receivers reside in the synchrodyning procedures usedto translate the final IF signal to baseband and in the symbol decodingprocedures. A receiver that is capable of receiving either VSB or QAMDTV signals is more economical in design if it does not duplicate thesimilar tuner circuitry prior to synchrodyning to baseband and thesimilar receiver elements used after the symbol decoding circuitry. Thechallenge is in optimally constructing the circuitry for synchrodyningto baseband and for symbol decoding to accommodate both DTV transmissionstandards and in arranging for the automatic selection of theappropriate mode of reception for the DTV transmission currently beingreceived.

DTV signal radio receivers are known of a type that usesdouble-conversion in the tuner followed by synchronous detection, havingbeen used during field testing of the HDTV system used duringdevelopment the ATSC standard. A frequency synthesizer generates firstlocal oscillations that are heterodyned with the received VSB DTVsignals to generate first intermediate frequencies (e. g., with 920 MHzcenter frequency and 922.69 MHz carrier). A passive LC bandpass filterselects these first intermediate frequencies from their imagefrequencies for amplification by a first intermediate-frequencyamplifier, and the amplified first intermediate frequencies are filteredby a ceramic resonator filter that rejects adjacent channel signals. Thefirst intermediate frequencies are heterodyned with second localoscillations to generate second intermediate frequencies (e. g., with46.69 MHz carrier); and a filter, which can be of surface-acoustic-wave(SAW) type, selects these second intermediate frequencies from theirimages and from remnant adjacent channel responses for amplification bya second intermediate-frequency amplifier. The response of the secondintermediate-frequency amplifier is supplied to a third mixer to besynchrodyned to baseband with third local oscillations of fixedfrequency. The third local oscillations of fixed frequency can besupplied in 0° phasing and in 90° phasing, thereby implementing separatein-phase and quadrature-phase synchronous detection procedures duringsynchrodyning. Synchrodyning is the procedure of multiplicatively mixinga modulated signal with a wave having a fundamental frequency the sameas the carrier of the modulated signal, being locked in frequency andphase thereto, and lowpass filtering the result of the multiplicativemixing to recover the modulating signal at baseband, baseband extendingfrom zero frequency to the highest frequency in the modulating signal.

Separately digitizing in-phase and quadrature-phase synchronousdetection results generated in the analog regime presents problems withregard to the synchronous detection results satisfactorily tracking eachother after digitizing; quantization noise introduces pronounced phaseerrors in the complex signal considered as a phasor. These problems canbe avoided in DTV signal radio receivers of types performing thein-phase and quadrature-phase synchronous detection procedures in thedigital regime. By way of example, the response of the secondintermediate-frequency amplifier is digitized at twice the Nyquist rateof the symbol coding. The successive samples are considered to beconsecutively numbered in order of their occurrence; and odd samples andeven samples are separated from each other to generate respective onesof the in-phase (or real) and quadrature-phase (or imaginary)synchronous detection results. Quadrature-phase (or imaginary)synchronous detection takes place after Hilbert transformation of oneset of samples using appropriate finite-impulse-response (FIR) digitalfiltering, and in-phase (or real) synchronous detection of the other setof samples is done after delaying them for a time equal to the latencytime of the Hilbert-transformation filter. The methods of locking thefrequency and phase of synchronous detection and the methods of lockingthe frequency and phase of symbol decoding differ in the VSB and QAM DTVreceivers.

These types of known DTV signal radio receiver present some problem inthe design of the tuner portion of the receiver because the respectivecarrier frequencies of VSB DTV signals and of QAM DTV signals are notthe same as each other. The carrier frequency of a QAM DTV signal is atthe middle of a 6-MHz-wide TV channel, but the carrier frequency of aVSB DTV signal nominally is about 310 kHz above the lower limitfrequency of the TV channel. Accordingly, the third local oscillationsof fixed frequency, which are used for synchrodyning to baseband, mustbe of different frequency when synchrodyning VSB DTV signals to basebandthan when synchrodyning QAM DTV signals to baseband. The 2.69 MHzdifference between the two carrier frequencies is larger than that whichis readily accommodated by applying automatic frequency and phasecontrol to the third local oscillator. A third oscillator that canswitchably select between two frequency-stabilizing crystals is apractical necessity. In such an arrangement, of course, alterations inthe tuner circuitry are involved with arranging for the automaticselection of the appropriate mode of reception for the DTV transmissioncurrently being received. The radio-frequency switching that must bedone reduces the reliability of the tuner. The RF switching and theadditional frequency-stabilizing crystal for the third oscillatorincrease the cost of the tuner appreciably.

Radio receivers for receiving digital television signals, in whichreceiver the final intermediate-frequency signal is somewhere in the 1-8MHz frequency range rather than at baseband, are described by C. B.Patel et alii in U.S. Pat. No. 5,479,449 issued Dec. 26, 1995, entitledDIGITAL VSB DETECTOR WITH BANDPASS PHASE TRACKER, AS FOR INCLUSION IN ANHDTV RECEIVER, and included herein by reference. The use ofinfinite-impulse response filters for developing complex digitalcarriers in such receivers is described by C. B. Patel et alii in U.S.Pat. No. 5,548,617 issued Aug. 20, 1996, entitled DIGITAL VSB DETECTORWITH BANDPASS PHASE TRACKER USING RADER FILTERS, AS FOR USE IN AN HDTVRECEIVER, and incorporated herein by reference. The use offinite-impulse response filters for developing complex digital carriersin such receivers is described by C. B. Patel et alii in allowed U.S.Pat. application Ser. No. 08/577,469 filed Dec. 22, 1995, entitledDIGITAL VSB DETECTOR WITH BANDPASS PHASE TRACKER USING NG FILTERS, ASFOR USE IN AN HDTV RECEIVER, and incorporated herein by reference. Thedesign of receivers for both QAM and VSB signals in which QAM/VSBreceivers both types of signal are processed through the sameintermediate-frequency amplifiers receivers is described by C. B. Patelet alii in U.S. Pat. No. 5,506,636 issued Apr. 9, 1996, entitled HDTVSIGNAL RECEIVER WITH IMAGINARY-SAMPLE-PRESENCE DETECTOR FOR QAM/VSB MODESELECTION, and incorporated herein by reference. U.S. Pat. No. 5,606,579issued Feb. 25, 1997 to C. B. Patel et alii and entitled DIGITAL VSBDETECTOR WITH FINAL I-F CARRIER AT SUBMULTIPLE OF SYMBOL RATE, AS FORHDTV RECEIVER is incorporated herein by reference. U.S. patentapplication Ser. No. 5,659,372 issued Aug. 19, 1997 by C. B. Patel etalii and entitled DIGITAL TV DETECTOR RESPONDING TO FINAL-IF SIGNAL WITHVESTIGIAL SIDEBAND BELOW FULL SIDEBAND IN FREQUENCY is incorporatedherein by reference. Allowed U.S. patent application Ser. No. 08/266,753filed Jun. 28, 1994 by C. B. Patel et alii and entitled RADIO RECEIVERFOR RECEIVING BOTH VSB AND QAM DIGITAL HDTV

SIGNALS is incorporated herein by reference. U.S. Pat. No. 5,715,012issued Feb. 3, 1998 to C. B. Patel et alii and entitled RADIO RECEIVERSFOR RECEIVING BOTH VSB AND QAM DIGITAL HDTV SIGNALS is incorporatedherein by reference. These patents and patent applications are allassigned to Samsung Electronics Co., Ltd., pursuant to employeeinvention agreements already in force at the time the inventionsdisclosed in these patents and patent applications were made.

In the QAM/VSB radio receivers described in U.S. Pat. Nos. 5,506,636 and5,715,012 the final intermediate-frequency signal is digitized, andsynchrodyne procedures to obtain baseband samples are carried out in thedigital regime. A tuner within the receiver includes elements forselecting one of channels at different locations in a frequency bandused for transmitting DTV signals, a succession of mixers for performinga plural conversion of signal received in the selected channel to afinal intermediate-frequency (IF) signal, a respectivefrequency-selective amplifier between each earlier one of the mixers inthat succession and each next one of said mixers in that succession, anda respective local oscillator for supplying oscillations to each of themixers. Each of these local oscillators supplies respective oscillationsof substantially the same frequency irrespective of whether the selectedDTV signal is a QAM signal or is a VSB signal. The final IF signal isdigitized, and thereafter there are differences in signal processingdepending on whether the selected DTV signal is a QAM signal or is a VSBsignal. These differences are accommodated in digital circuitryincluding QAM synchrodyning circuitry and VSB synchrodyning circuitry.The QAM synchrodyning circuitry generates real and imaginary samplestreams of interleaved QAM symbol code, by synchrodyning the digitizedfinal IF signal to baseband providing it is a QAM signal and otherwiseprocessing the digitized final IF signal as if it were a QAM signal tobe synchrodyned to baseband. The VSB synchrodyning circuitry generates areal sample stream of interleaved VSB symbol code, by synchrodyning thedigitized final IF signal to baseband providing it is a VSB signal andotherwise processing the digitized final IF signal as if it were a VSBsignal to be synchrodyned to baseband. A detector determines by sensingthe presence of a pilot carrier accompanying a DTV signal of VSB typewhether or not the final IF signal is a VSB signal to generate a controlsignal, which is in a first condition when the final IF signalapparently is not a VSB signal and is in a second condition when thefinal IF signal apparently is a VSB signal. Responsive to the controlsignal being in its first condition, the radio receiver is automaticallyswitched to operate in a QAM signal reception mode; and responsive tothe control signal being in its second condition, the radio receiver isautomatically switched to operate in a VSB signal reception mode.

U.S. Pat. No. 5,506,636, U.S. patent application Ser. No. 08/266,753 andU.S. patent application Ser. No. 08/614,471 were written presuming thatthe carrier frequency of a VSB DTV signal would be 625 kHz above lowestchannel frequency, as earlier proposed by a subcommittee of the AdvancedTelevision Systems Committee. This specification presumes that thecarrier frequency of a VSB DTV signal is about 310 kHz above lowestchannel frequency, as specified in Annex A of the Digital TelevisionStandard published Sep. 16, 1995.

The carrier of the final IF signal is preferably one prescribedsubharmonic of a multiple of the symbol frequencies of both the QAM andVSB signals if the selected DTV signal is a QAM signal and is anotherprescribed subharmonic of that multiple if the selected DTV signal is aVSB signal. When the carrier frequency of a VSB DTV signal is nominally310 kHz above lowest channel frequency, these prescribed subharmonicsshould differ in frequency by substantially 2.69 MHz. Digitizing thefinal IF signal at this multiple of the symbol frequencies of both theQAM and VSB signals facilitates the generation of the digital carriersused to synchrodyne the QAM and VSB final IF signals to baseband. Thismultiple of the symbol frequencies of both the QAM and VSB signalsshould be low enough that digitization is practical, but is preferablyabove Nyquist rate.

In one type of these QAM/VSB radio receivers the prescribed subharmonicof a multiple of the symbol frequency of the QAM signal is substantially2.69 MHz higher in frequency than the prescribed subharmonic of amultiple of the symbol frequency of said VSB signal. In a preferred suchreceiver the frequency of the QAM carrier in the final IF signal is 5.38MHz, the first subharmonic of 10.76 MHz, and the frequency of the VSBsignal carrier in the final IF signal is 2.69 MHz, the third subharmonicof 10.76 MHz.

In another type of these QAM/NVSB radio receivers the prescribedsubharmonic of a multiple of the symbol frequency of the QAM signal issubstantially 2.69 MHz lower in frequency than the prescribedsubharmonic of a multiple of the symbol frequency of the VSB signal. TheVSB signal having its full sideband below carrier frequency in the finalIF signal is sampled with better resolution in such embodiments of theinvention. In a preferred such embodiment the frequency of the QAMcarrier in the final IF signal is 5.38 MHz, the first subharmonic of10.76 MHz, and the frequency of the VSB signal carrier in the final IFsignal is 8.07 MHz, the third subharmonic of the third harmonic of 10.76MHz.

When synchrodyning is done in the digital regime, the generation of thedigital carriers from read-only memory (ROM) is facilitated bydigitizing the final IF signal of both the QAM and VSB signals at asampling rate that is a multiple of each of their symbol rates.Phase-locking the frequency of the carrier used for synchrodyning to thecarrier of the QAM or VSB signals to baseband is thereby facilitated.

Digitizing the QAM and VSB DTV signals at multiples of their symbolrates facilitates symbol synchronization, whether synchrodyning is donein the digital regime as described by Patel et alii or is done in theanalog regime. In order to perform symbol synchronizationsatisfactorily, digital samples must be provided at a sample rate atleast twice symbol rate. Supplying digital samples at a rate higher thansymbol rate will increase the number of taps in the digital filters usedfor channel equalization of the baseband DTV signal, since the number ofsample times in a ghost of any particular duration will increase indirect ratio to how many times the symbol rate the sampling rate is.Digitizing a QAM or VSB DTV signal at a multiple M times N of its symbolrate, M being a positive number at least one and N being a positiveinteger at least 2 allows the N:1 decimation of the digital DTV basebandsignal before performing channel equalization thereof, so long as theNyquist criterion for transmitting symbols is satisfied in the decimateddigital signal.

SUMMARY OF THE INVENTION

In accordance with an aspect of the invention, the digitized DTV signalis decimated before performing channel equalization thereof, whichreduces the number of samples in the kernels of the digital filters forperforming channel equalization and reduces the cost of the DTV receiversubstantially.

Decimation of a digitized VSB signal to a sampling rate less than twiceits symbol rate (i. e., particularly to a sampling rate equal to itssymbol rate) requires that symbol synchronization take place before thedecimation procedure, in order that symbol information not be lost inthe decimation procedure. An aspect of the invention is performingsymbol synchronization before that decimation procedure. A furtheraspect of the invention is a method of performing the symbolsynchronization by steps of: extracting a signal associated with therequired symbol rate and timing from the baseband DTV data, detectingfrequency and phase error between the extracted signal and the samplingrate of the analog-to-digital converter in the radio receiver portion ofthe DTV receiver, applying the detected frequency and phase error to acontrolled oscillator as an automatic frequency and phase controlsignal, and generating from the oscillations of that controlledoscillator the sample clock signal determining the sampling rate of theanalog-to-digital converter.

The invention is embodied in a digital television (DTV) receiverincluding a radio receiver portion for selecting a channel forreception, for converting DTV signal in the selected channel tointermediate frequencies for filtering and amplification, and forsynchrodyning an analog final intermediate-frequency output signalresulting from that filtering and amplification to baseband, thereby togenerate a baseband signal. The DTV receiver may be one designed forreceiving QAM DTV signal, VSB DTV signal or both types of DTV signal. Ananalog-to-digital converter (ADC) is included in this radio receiverportion for sampling one of the signals therein and digitizing it sothat the baseband signal is supplied from the radio receiver portion asa first stream of digital samples descriptive of the baseband signal. Asample clock generator is connected for supplying a sample clock signalto time the sampling by the ADC so that the first stream of digitalsamples has a sample rate substantially equal to a prescribed multipleMN times the symbol rate of the DTV signal. MN is the product of apositive number M greater than one and of a positive integer N at leasttwo. A decimator is connected for receiving the first stream of digitalsamples and generating in response thereto a second stream of digitalsamples at a sample rate that is one-N^(th) that of the first stream ofdigital samples. The number of taps required in a channel equalizer forperforming channel equalization to generate a channel equalizer responseis reduced by the N:1 decimation of the second stream of digitalsamples. The resultant saving in digital multipliers provides asubstantial benefit in cost and reliability. A symbol synchronizer isincluded in the DTV receiver for correcting the symbol phase error inthe channel equalizer response; and a symbol decoder is included in theDTV receiver for decoding symbols in the channel equalizer response, ascorrected for symbol phase error, to recover groups of bitscorresponding to decoded symbols.

In a preferred embodiment of this type of DTV receiver the sample clockgenerator comprises an oscillator for supplying oscillations at afrequency controlled by an automatic frequency and phase control signal,and circuitry for generating the sample clock signal at a rateresponsive to the oscillation frequency; and the symbol synchronizercomprises an FIR filter for selecting only signal of a prescribedsubharmonic of symbol rate from the first stream of digital samples, andan automatic frequency and phase control detector for detectingfrequency and phase error between the sampling rate of the ADC and theprescribed subharmonic of the symbol rate as selected in the response ofthe FIR filter.

In another aspect of invention, a controlled oscillator used to timesamples supplied from a sample clock generator is synchronized with thesymbols in a baseband DTV signal, by developing anautomatic-frequency-and-phase-control (AFPC) signal for the controlledoscillator from the symbol code despite the baud frequency being absenttherefrom. This is done by subjecting the baseband-DTV-signal symbolcode to a narrow bandpass finite-impulse-response (FIR) digital filtertimed by the samples supplied from the sample clock generator. Anon-linear procedure that will generate second harmonics, such assquaring, is applied to the narrow bandpass FIR digital filter responseto regenerate the baud frequency accompanied by a noise spectrum. Anautomatic-frequency-and-phase-control detector detects the error of theoscillation frequency of the controlled oscillator respective to theregenerated baud frequency and provides a lowpass filtered response tothe error signal applied to the controlled oscillator as its AFPCsignal.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 is a block schematic diagram of initial portions of a digitaltelevision (DTV) receiver of a type that can embody the invention,including circuitry for detecting symbols in a DTV signal of QAM type,circuitry for detecting symbols in a DTV signal of VSB type, and anamplitude-and-group-delay equalizer for symbols selected from thecircuitry for detecting symbols in a DTV signal of QAM type and thecircuitry for detecting symbols in a DTV signal of VSB type.

FIG. 2 is a block schematic diagram of the remaining portions of DTVreceiver of a type that can embody the invention, which are not shown inFIG. 1.

FIG. 3 is a detailed block schematic diagram of digital circuitry forsynchrodyning QAM DTV signals to baseband, of digital circuitry forsynchrodyning VSB DTV signals to baseband, and of circuitry associatedwith applying input signals to that QAM and VSB synchrodyning circuitry,as used in a DTV signal radio receiver of the type shown in FIGS. 1 and2.

FIG. 4 is a detailed block schematic diagram of circuitry for providingthe sample clock generator, the look-up table read-only memories (ROMs)for supplying digital descriptions of the complex carriers used forsynchrodyning digital QAM signals and digital VSB signals at final IFsignal frequencies each to baseband, and the address generators forthose ROMs, which circuitry is included in certain DTV signal radioreceivers of the type that can embody the invention.

FIG. 5 is a detailed block schematic diagram of circuitry similar tothat of FIG. 4, modified so that the address generator for the ROMssupplying digital descriptions of the complex carrier used forsynchrodyning digital QAM signals to baseband and the ROMs supplyingdigital descriptions of the complex carrier used for synchrodyningdigital VSB signals to baseband share an address counter in common.

FIG. 6 is a detailed block schematic diagram of circuitry for convertingdigital samples to complex form in DTV signal radio receivers embodyingthe invention, which circuitry includes a Hilbert transformation filterfor generating imaginary samples from real samples, and which includesdelay compensation for the real samples equivalent to the latency ofthat filter.

FIG. 7 is a detailed block schematic diagram of a pair of all-passdigital filters of infinite-impulse-response (IIR) type designed basedon Jacobian elliptic functions and exhibiting a constant π/2 differencein phase response for the digitized bandpass signals, as are known inthe prior art and can be employed for converting digital samples tocomplex form in DTV signal radio receivers embodying the invention.

FIGS. 8 and 9 are block schematic diagrams of changes that can be madethe filter circuitry of FIG. 7 to remove redundant delay.

FIG. 10 is a detailed block schematic diagram of a pair of all-passdigital filters of finite-impulse-response (FIR) type exhibiting aconstant π/2 difference in phase response for the digitized bandpasssignals, as can be employed for converting digital samples to complexform in DTV signal radio receivers embodying the invention.

FIG. 11 is a graph of the constraints on the final intermediatefrequencies to which the carriers of a QAM DTV signal and a VSB DTVsignal can be frequency translated, when the carrier of a VSB DTV signalis lower in frequency than the carrier of a QAM DTV signal in the finalIF signal, so the full sideband of the VSB DTV signal is higher infrequency than its vestigial sideband in the final IF signal, and whenthe sample rate during digitization is constrained to 21.52 * 10⁶samples per second.

FIG. 12 is a graph of the constraints on the final intermediatefrequencies to which the carriers of a QAM DTV signal and a VSB DTVsignal can be frequency translated, when the carrier of a VSB DTV signalis higher in frequency than the carrier of a QAM DTV signal in the finalIF signal, so the full sideband of the VSB DTV signal is lower infrequency than its vestigial sideband in the final IF signal, and whenthe sample rate during digitization is constrained to 21.52 * 10⁶samples per second.

FIG. 13 is a block schematic diagram of portions of another type of DTVreceiver that can embody the invention, which portions are not shown inFIG. 1 and differ from those of FIG. 2 in the way data sync recovery isprovided for.

In the block schematic diagrams, clock or control signal connections areshown in dashed line, where it is desired to distinguish them fromconnections for the signals being controlled. To avoid overcomplexity inthe block schematic diagrams, some shimming delays necessary in thedigital circuitry are omitted, where a need for such shimming delay isnormally taken into account by a circuit or system designer.

DETAILED DESCRIPTION

FIG. 1 shows a tuner 5 comprising elements 11-21 that selects one ofchannels at different locations in the frequency band for DTV signalsand performs plural frequency conversion of the selected channel to afinal intermediate-frequency signal in a final intermediate-frequencyband. FIG. 1 shows a broadcast receiving antenna 6 arranged to capturethe DTV signals for the tuner 5. Alternatively, the tuner 5 can beconnected for receiving DTV signals from a narrowcast receiving antennaor from a cablecast transmission system.

More particularly, in the tuner 5 shown in FIG. 1, a channel selector 10designed for operation by a human being determines the frequency offirst local oscillations that a frequency synthesizer 11, whichfunctions as a first local oscillator, furnishes to a first mixer 12 forheterodyning with DTV signals received from the antenna 6 or analternative source of such signals. The first mixer 12 upconverts thereceived signals in the selected channel to prescribed firstintermediate frequencies (e.g., with 922.69 MHz carrier), and an LCfilter 13 is used to reject the unwanted image frequencies thataccompany the upconversion result supplied from the first mixer 12. Thefirst intermediate-frequency signal resulting from the upconversion,supplied as the filter 13 response, is applied as the input signal to afirst intermediate-frequency amplifier 14, which supplies amplifiedfirst IF signal for driving a first surface-acoustic-wave (SAW) filter15 or a filter constructed from ceramic resonators. The upconversion tothe rather high-frequency first intermediate frequencies facilitates theSAW filter 15 having a large number of poles and zeroes. The SAW filter15 passband is designed to pass those frequencies obtained by convertingfrequencies extending from the lower limit frequency of the televisionchannel up to about 300 kHz of the upper limit frequency of thetelevision channel. Preferably the SAW filter 15 is designed to rejectthe frequency-modulated sound carrier of any co-channel interfering NTSCanalog TV signal. Second local oscillations from a second localoscillator 16 are supplied to a second mixer 17 for heterodyning withthe response of the first SAW filter 15, to generate second intermediatefrequencies (e.g., with 46.69 MHz carrier). A second SAW filter 18 isused for rejecting the unwanted image frequencies that accompany thedown-conversion result supplied from the second mixer 17. During theperiod of transition from NTSC television transmissions to digitaltelevision transmissions, the second SAW filter 18 will usually includetraps for sound and video carriers of adjacent-channel NTSC televisiontransmissions. The second IF signal supplied as the response of thesecond SAW filter 18 is applied as input signal to a secondintermediate-frequency amplifier 19, which generates an amplified secondIF signal response to its input signal. Oscillations from a third localoscillator 20 are heterodyned with the amplified second IF signalresponse in a third mixer 21. The plural-conversion tuner 5 as thus fardescribed resembles those previously proposed by others, except that thefrequency of the oscillations from the third local oscillator 20 ischosen such that the third mixer 21 supplies a thirdintermediate-frequency signal response.

This third IF signal response is the final intermediate-frequency outputsignal of the tuner 5, which is supplied to a subsequentanalog-to-digital converter (ADC) 22 for digitization. This final IFsignal occupies a frequency band 6 MHz wide, the lowest frequency ofwhich is above zero frequency. The lowpass analog filtering of the thirdmixer 21 response done in the ADC 22 as a preliminary step inanalog-to-digital conversion suppresses the image frequencies of thethird intermediate frequencies, and the second SAW filter 18 has alreadyrestricted the bandwidth of the third intermediate-frequency signalspresented to the ADC 22 to be digitized; so the ADC 22 functions as abandpass analog-to-digital converter. The sampling of the lowpass analogfilter response in the ADC 22 as the next step in analog-to-digitalconversion is done responsive to pulses in a first clock signal suppliedfrom a sample clock generator 23.

The sample clock generator 23 preferably includes a crystal oscillatorcapable of frequency control over a relatively narrow range forgenerating cissoidal oscillations at a multiple of symbol rate. Asymmetrical clipper or limiter generates a square-wave response to thesecissoidal oscillations to generate the first clock signal, which the ADC22 uses to time the sampling of the final IF signal after filtering tolimit bandwidth. The frequency of the cissoidal oscillations generatedby the crystal oscillator in the sample clock generator 23 can bedetermined by an automatic frequency and phase control (AFPC) signaldeveloped in response to components of the received DTV signal that aresubharmonics of symbol or baud rate, for example, as will be describedin detail further on in this specification. The pulses in the firstclock signal recur at a 21.52 * 10⁶ samples-per-second rate, twice the10.76 * 10⁶ symbols-per-second symbol rate for VSB signals and fourtimes the 5.38 * 10⁶ symbols-per-second symbol rate for QAM signals. Atthis 21.52 * 10⁶ samples-per-second clock rate, placing the final IFsignal so its mid-frequency is above 5.38 MHz reduces the number of21.52 * 10⁶ samples-per-second rate samples in the QAM carrier to lessthan four, which undesirably reduces the uniformity of synchrodyneresponse supplied for symbol decoding.

The ADC 22 supplies real digital responses of 10-bit or so resolution tothe samples of the band-limited final IF signal, which digital responsesare converted to complex digital samples by the circuitry 24. Variousways to construct the circuitry 24 are known. The imaginary digitalsamples at the QAM carrier frequency may be generated using a Hilberttransformation filter, for example, as described in U.S. Pat. No.5,479,449. If the frequency band 6 MHz wide occupied by the final IFsignal has a lowest frequency of at least a megaHertz or so, it ispossible to keep the number of taps in the Hilbert transformation filterreasonably small and thus keep the latency time of the filter reasonablyshort. Other ways to construct the circuitry 24 described in U.S. Pat.No. 5,548,617 rely on the differential delay between the responses oftwo infinite-impulse-response (IIR) filters being substantially equal to90.degree. phase shift at all frequencies. Still other ways to constructthe circuitry 24 rely on the differential delay between the responses oftwo finite-impulse-response (FIR) filters being substantially equal to90° phase shift at all frequencies.

In the FIG. 1 receiver circuitry the complex digital samples of final IFsignal supplied from the circuitry 24 are applied to circuitry 25 forsynchrodyning the QAM signal to baseband. The circuitry 25 supplies astream of real samples and a stream of imaginary samples in parallel toa symbol de-interleaver 26, to provide baseband description of the QAMmodulating signal. The QAM synchrodyning circuitry 25 receivescomplex-number digital descriptions of two phasings of the QAM carrier,as translated to final intermediate frequency and in quadraturerelationship with each other, from read-only memory 27. ROM 27, whichcomprises sine and cosine look-up tables for QAM carrier frequency, isaddressed by a first address generator 28. The first address generator28 includes an address counter (not explicitly shown in FIG. 1) forcounting the recurrent clock pulses in the first clock signal generatedby the sample clock generator 23. The resulting address count isaugmented by a symbol phase correction term generated by QAM de-rotatorcorrection circuitry, thereby to generate the addressing for the ROM 27.The QAM synchrodyne circuitry 25, the first address generator 28, andthe operation of each will be explained in greater detail further on inthis specification.

In the FIG. 1 receiver circuitry the complex digital samples of final IFsignal supplied from the circuitry 24 are also applied to circuitry 30for synchrodyning the VSB signal to baseband. The VSB synchrodyningcircuitry 30 supplies streams of samples descriptive of real andimaginary components of the vestigial-sideband modulating signal assynchrodyned to baseband. The VSB synchrodyning circuitry 30 receivescomplex-number digital descriptions of two phasings of the VSB carrier,as translated to final intermediate frequency and in quadraturerelationship with each other, from read-only memory 31. ROM 31, whichcomprises sine and cosine look-up tables for VSB carrier frequency, isaddressed by a second address generator 32. The second address generator32 includes an address counter (not explicitly shown in FIG. 1) forcounting the recurrent clock pulses in the first clock signal generatedby the sample clock generator 23. In preferred embodiments of theinvention this address counter is the same address counter used by thefirst address generator 28. The resulting address count is augmented bya symbol phase correction term generated by symbol phase correctioncircuitry, thereby to generate the addressing for the ROM 31. The VSBsynchrodyne circuitry 30, the second address generator 32, and theoperation of each will be explained in greater detail further on in thisspecification.

A digital-signal multiplexer 33 functions as a synchrodyne resultselector that selects as its response either a first or a second one oftwo complex digital input signals supplied thereto, the selection beingcontrolled by a detector 34 for detecting the zero-frequency term of thereal samples from the VSB synchrodyne circuitry 30. When thezero-frequency term has essentially zero energy, indicating the absenceof pilot carrier signal that accompanies a VSB signal, the multiplexer33 selectively responds to its first complex digital input signal, whichis the de-interleaved QAM synchrodyne-to-baseband result supplied fromthe de-interleaver 26. When the zero-frequency term has substantialenergy, indicating the presence of pilot carrier signal that accompaniesa VSB signal, the multiplexer 33 selectively responds to its secondcomplex digital input signal comprising the real and imaginarycomponents of the baseband response of the VSB synchrodyne circuitry 30.

The response of the synchrodyne result selection multiplexer 33 isresampled in response to a second clock signal from the sample clockgenerator 23 in 2:1 decimation circuitry 35, to reduce the sample rateof complex baseband response down to the 10.76 MHz VSB symbol rate,which is twice the 5.38 MHz QAM symbol rate. That is, the stream of realdigital samples and the stream of imaginary digital samples are bothdecimated 2:1. The 2:1 decimation of the multiplexer 33 response priorto its application as input signal to an amplitude-and-group-delayequalizer 36 reduces the hardware requirements on the equalizer.Alternatively, rather than 2:1 decimation circuitry 35 being used afterthe synchrodyne result selection multiplexer 33, the baseband responsesof the QAM synchrodyne circuitry 25 and of the VSB synchrodyne circuitry30 can each be resampled in response to a second clock signal from thesample clock generator 23 to carry out 2:1 decimation before thesynchrodyne result selection multiplexer 33.

FIG. 2 shows the amplitude-and-group-delay equalizer 36, which convertsa baseband response with an amplitude-and-phase-versus-frequencycharacteristic that tends to cause inter-symbol error to an improvedamplitude-versus-frequency characteristic that minimizes the likelihoodof inter-symbol error. The amplitude-and-group-delay equalizer 36 can bea suitable one of the monolithic ICs available off-the-shelf for use inequalizers. Such an IC includes a multiple-tap digital filter used foramplitude-and-group-delay equalization, the tap weights of which filterare programmable; circuitry for selectively accumulating a trainingsignal and temporarily storing the accumulation results; and amicrocomputer for calculating updated tap weights of the multiple-tapdigital filter used for amplitude-and-group-delay equalization.

When the DTV signal being received is of VSB type, training signal iscontained in the initial data segment of each data field. Themicrocomputer is programmed for comparing the temporarily storedaccumulation results with the ideal training signal as known a prioriand establishing a set of weighting coefficients for the multiple-tapdigital filter used for amplitude-and-group-delay equalization.Thereafter, better to compensate for changing multipath conditions suchas caused by overflying aircraft, weighting coefficients may be updatedon a more frequent basis using decision-directed equalizationtechniques, such as those disclosed by the inventors and Dr. Jian Yangin U.S. Pat. No. 5,648,987 issued Jul. 15, 1997 and entitledRAPID-UPDATE ADAPTIVE CHANNEL-EQUALIZATION FILTERING FOR DIGITAL RADIORECEIVERS, SUCH AS HDTV RECEIVERS. When the DTV signal being received isof QAM type, unless provision is made for inclusion of a trainingsignal, decision-directed equalization techniques have to be used ifequalization is to be effected. The establishment of a satisfactory setof initial weighting coefficients takes more time than when a trainingsignal is available. If the DTV receiver remains in place during periodsof operation and non-operation, the time required to establish asatisfactory set of initial weighting coefficients when a DTV channel isreturned can be reduced by if the last determined set of weightingcoefficients for that DTV channel have been stored in memory.

Both the real and the imaginary responses of theamplitude-and-group-delay equalizer 36 are applied as input signal totwo-dimensional symbol decoding circuitry 37, which performs the symboldecoding that recovers symbol-decoded digital data streams from aQAM-origin signal. Presuming that the QAM-origin signal contains datasynchronizing information corresponding to the data synchronizinginformation in the VSB-origin signal, one of these symbol-decodeddigital data streams is a trellis-decoded digital data stream suppliedfor further data processing, and another of these symbol-decoded digitaldata streams is generated by data-slicing without subsequent trellisdecoding. Data synchronizing information is extracted from this lattersymbol-decoded digital data stream and is employed for controlling theprocessing of the QAM-origin data by the receiver.

The real response of the amplitude-and-group-delay equalizer 36 isapplied as input signal to one-dimensional symbol decoding circuitry 38,which performs the symbol decoding that recovers symbol-decoded digitaldata streams from a VSB-origin signal. A VSB signal in accordance withthe ATSC standard uses trellis coding of the data in all data segmentsexcept the initial data segment of each data field, which contains fieldsynchronization code groups that are not subject to trellis coding. Asin the prior art, one of the symbol-decoded digital data streams thatthe symbol decoding circuitry 38 supplies, which is to be employed forfurther data processing is generated by trellis-decoding the results ofdata-slicing procedures, and optimal Viterbi decoding techniques arecustomarily employed. As in the prior art, another of the symbol-decodeddigital data streams that the symbol decoding circuitry 38 supplies,which is to be employed for controlling data handling by the receiverresponsive to synchronization information contained in the receivedVSB-origin signal, is generated using data-slicing procedures withoutsubsequent trellis decoding. The symbol decoding circuitry 38 preferablydeparts from usual prior-art practice by utilizing data-slicingtechniques similar to those described in allowed U.S. patent applicationSer. No. 08/746,520 filed Nov. 12, 1996, entitled DIGITAL TELEVISIONRECEIVER WITH ADAPTIVE FILTER CIRCUITRY FOR SUPPRESSING NTSC CO-CHANNELINTERFERENCE, and incorporated herein by reference.

A digital-signal multiplexer 39 functions as a data source selector thatselects as its response either a first or a second one of two digitalinput signals thereto, the selection being controlled by the detector 34for detecting the zero-frequency term of the real samples from the VSBsynchrodyne circuitry 30. When the zero-frequency term has essentiallyzero energy, indicating the absence of pilot carrier signal thataccompanies a VSB signal, the multiplexer 39 selectively responds to itsfirst digital input signal, selecting as the source of its digital dataoutput the two-dimensional symbol decoding circuitry 37 that decodes thesymbols received in the QAM signal. When the zero-frequency term hassubstantial energy, indicating the presence of pilot carrier signal thataccompanies a VSB signal, the multiplexer 39 selectively responds to itssecond digital input signal, selecting as the source of its digital dataoutput the one-dimensional symbol decoding circuitry 38 that decodes thesymbols received in the VSB signal.

The data selected by the data source selection multiplexer 39 areapplied to a data de-interleaver 40 as its input signal, and thede-interleaved data supplied from the data de-interleaver 40 are appliedto a Reed-Solomon decoder 41. The data de-interleaver 40 is oftenconstructed within its own monolithic IC and is made so as to respond tothe output indications from the pilot carrier presence detector 34 toselect the de-interleaving algorithm suitable to the DTV signalcurrently being received, whether it be of QAM or VSB type; this is amere matter of design. The Reed-Solomon decoder 41 is often constructedwithin its own monolithic IC and is made so as to respond to the outputindications from the pilot carrier presence detector 34 to select theappropriate Reed-Solomon decoding algorithm for the DTV signal currentlybeing received, whether it be of QAM or VSB type; this also is a merematter of design. Error-corrected data are supplied from theReed-Solomon decoder 41 to a data de-randomizer 42, which responds tothese data for regenerating a signal randomized prior to transmission tothe DTV receiver, which regenerated signal comprises packets of data fora packet sorter 43. The data de-randomizer 42 is made so as to respondto the output indications from the pilot carrier presence detector 34 toselect the appropriate data de-randomizing algorithm for the DTV signalcurrently being received, whether it be of QAM or VSB type; theselection of these algorithms is a mere matter of design, too.

First data synchronization recovery circuitry 44 recovers the datasynchronizing information included in the data output of thetwo-dimensional symbol decoding circuitry decoder 37, and second datasynchronization recovery circuitry 45 recovers the data synchronizinginformation included in the data output of the one-dimensional symboldecoding circuitry 38. A data sync selector 46 selects between the datasynchronizing information as provided by the data sync recoverycircuitry 44 and as provided by the data sync recovery circuitry 45, theselection being controlled by the detector 34 for detecting thezero-frequency term of the real samples from the VSB synchrodynecircuitry 30. When the zero-frequency term has essentially zero energy,indicating the absence of pilot carrier signal that accompanies a VSBsignal, the data sync selector 46 selects for its output signals thedata synchronizing information provided by the data sync recoverycircuitry 44. When the zero-frequency term has substantial energy,indicating the presence of pilot carrier signal that accompanies a VSBsignal, the data sync selector 46 selects for its output signals thedata synchronizing information provided by the data sync recoverycircuitry 45.

When the data sync selector 46 selects for its output signals the datasynchronizing information provided by the data sync recovery circuitry45, the initial data lines of each data field are selected forapplication to the amplitude-and-group-delay equalizer 36 as trainingsignal. The occurrences of the 511-sample PN sequence can be detectedwithin the data sync recovery circuitry 45 to provide data-fieldindexing information to the data sync selector 46. Alternatively, theoccurrences of two or three consecutive 63-sample PN sequences aredetected within the data sync recovery circuitry 45 to providedata-field indexing information to the data sync selector 46.

The standards for a QAM DTV signal are not as well defined at this timeas the standards for a VSB DTV signal. A 32-state QAM signal providessufficient capacity for a single HDTV signal, without having to resortto compression techniques outside MPEG standards, but commonly somecompression techniques outside MPEG standards are employed to encode thesingle HDTV signal as a 16-state QAM signal. Typically, the occurrenceof a prescribed 24-bit word is detected by the data sync recoverycircuitry 44 to generate data-field indexing information for applicationto the data sync selector 46. A multiplexer within the data syncselector 46 selects between the data-field indexing informationrespectively supplied by the data sync recovery circuitry 44 and thedata sync recovery circuitry 45; the data-field indexing informationthus selected is supplied to the data de-interleaver 40, theReed-Solomon decoder 41, and the data de-randomizer 42. At the time thisspecification is written there is no training signal included in the QAMDTV signal. Accordingly, in response to the VSB pilot carrier presencedetector 34 indicating the absence of pilot carrier, theamplitude-and-group-delay equalizer 36 is conditioned to usedecision-directed equalization techniques that do not depend on atraining signal; and the VSB training signal selected by the data syncrecovery circuitry 45 is wired through the data sync selector 46 withoutneed for a multiplexer. Also, there is no data line synchronizationsignal for QAM DTV transmission, at least not a data linesynchronization signal selected as a standard. The data sync recoverycircuitry 44 includes counting circuitry for counting the samples ineach data field to generate intra-data-field synchronizing information.This intra-data-field synchronizing information and the intra-data-fieldsynchronizing information (such as data line count) generated by thedata sync recovery circuitry 45 are selected between by appropriatemultiplexers in the data sync selector 46, for application to the datade-interleaver 40, the Reed-Solomon decoder 41, and the datade-randomizer 42, as required.

FIG. 2 of the U.S. Pat. No. 5,506,636 drawing shows a variant of thesymbol decoding circuitry 37 in which variant the trellis decodingresults and the symbol-decoded data synchronization aretime-division-multiplexed onto a single bus for application to the datasource selector 39 and to the first data sync recovery circuitry 44.FIG. 2 of the U.S. Pat. No. 5,506,636 drawing also shows a variant ofthe symbol decoding circuitry 38 in which variant the trellis decodingresults and the symbol-decoded data synchronization aretime-division-multiplexed onto a single bus for application to the datasource selector 39 and to the second data sync recovery circuitry 45. Asin the embodiment shown in FIG. 2 of the drawing for this specification,the first data sync recovery circuitry 44 and the second data syncrecovery circuitry 45 perform data synchronization by match filtering ofsymbol decoding results. If the initial data segment of each data fieldper the ATSC specification for VSB broadcasting is simply recoded usingthe symbol codes for QAM cablecasting, data synchronization can beperformed after symbol decoding the QAM signal by looking forsymbol-decoded PN sequence information. Data synchronization is shown inFIG. 2 as being performed after symbol decoding the VSB signal; this isdone by looking for symbol-decoded PN sequence information. If theinitial data segment of each data field per the ATSC specification forVSB broadcasting is simply recoded using the symbol codes for QAMcablecasting, then, in a modification of the FIG. 2 DTV receivercircuitry, data synchronization can be performed after symbol decodingusing the same apparatus during both VSB signal reception and during QAMsignal reception.

Data synchronization during VSB signal reception can alternatively beaccomplished before symbol decoding, using match filters that generatespike responses to the PN sequences in the decimator 35 response or inthe equalizer 36 response. The filters that generate spike responses tosynchronization code sequences are preferably supplied input signals atthe decimated sample rate, rather than input signals being theundecimated responses of synchrodyne circuits 29 and 30, in order toreduce the number of samples in the respective kernel of each matchfilter. The filters that generate spike responses to synchronizationcode sequences are preferably connected to receive the equalizer 36response to reduce the effect that multi-path reception has on datasynchronization.

FIG. 13 shows a modification of the FIG. 2 portions of the DTV receiverin which the data sync recovery circuitry 45 for recovering datasynchronization from symbol decoding results is replaced by second datasync recovery circuitry 450 employing match filters for recovering datasynchronization from the equalizer 36 response. The initial data segmentin each data field can be detected using a match filter for one of thePN sequences in those initial data segments, a match filter for the511-sample PN sequence being preferred because of the higher energy ofits auto-correlation response providing better selectivity than theauto-correlation response of a match filter for the 63-sample PNsequence. The match filter for the PN sequence can serve dual purpose,being used to identify the positions of ghosts during the calculation offilter coefficients for the equalizer 36. U.S. Pat. No. 5,594,506 issuedJan. 14, 1997 to J. Yang and entitled LINE SYNC DETECTOR FOR DIGITALTELEVISION RECEIVER describes a preferred form for detecting the4-symbol segment sync code group located at the beginning of each datasegment.

The packet sorter 43 sorts packets of data for different applications,responsive to header codes in the successive packets of data. Packets ofdata descriptive of the audio portions of the DTV program are applied bythe packet sorter 43 to a digital sound decoder 47. The digital sounddecoder 47 supplies left-channel and right-channel stereophonic soundsignals to a plural-channel audio amplifier 48 that drives the pluralityof loudspeakers 49, 50. Packets of data descriptive of the videoportions of the DTV program are applied by the packet sorter 43 to anMPEG decoder 51, such as of MPEG-2 type. The MPEG decoder 51 supplieshorizontal (H) and vertical (V) synchronizing signals to kinescopedeflection circuitry 52 that provides for the raster scanning of theviewing screen of a kinescope 53. The MPEG decoder 51 also suppliessignals to the kinescope driver amplifiers 54 for applying amplified red(R), green (G) and blue (B) drive signals to the kinescope 53. Invariations of the DTV receiver shown in FIGS. 1 and 2, a differentdisplay device may be used instead of or in addition to the kinescope53, and the sound recovery system may be different, consisting of but asingle audio channel, or being more elaborate than a simple stereophonicreproduction system.

Referring back to FIG. 1, in order that ROMs 27 and 31 can be used togenerate digital complex-number descriptions of the QAM and VSB signalcarriers as translated to respective final intermediate frequencies, inresponse to addressing generated by counting first clock signals,provision must be made to lock the one those final intermediatefrequencies that is the carrier of the currently received DTV signal toa submultiple of a multiple of the first clock signal frequency. Thatis, those final intermediate frequencies must be in whole number ratioswith the first clock signal frequency. An automatic phase and frequencycontrol (AFPC) signal is developed in the digital circuitry followingthe analog-to-digital converter 22 and is used to control the frequencyand phase of one of the local oscillators 11, 16 and 20 in the tuner.Preferably, in order that alignment of the second IF signal with thesecond SAW filter 18 can be readily assured, a fixed-frequency thirdlocal oscillator 20 is used, and the frequency and phase of theoscillations the second local oscillator 16 provides are controlled. Thesecond SAW filter 18 usually includes traps for adjacent-channel signalcomponents, in which case proper alignment of the second IF signalbetween these traps is important for preserving its integrity. Thesymbol clocking is made to exhibit a high degree of frequency stability.By locking the carrier of the final intermediate-frequency (IF) signalin frequency and phase to a submultiple of a multiple of the symbolclock frequency, the AFPC for correcting frequency and phase error inthe carrier as translated to a final intermediate frequency invariablyoperates to correct dynamic symbol phase error as well, eliminating theneed for a separate phase tracker to correct dynamic symbol phase error.

FIG. 1 denominates a digital multiplexer 55 as “AFPC selector”. Themultiplexer 55 responds to the pilot carrier presence detector 34indicating that a pilot carrier is included in the currently receivedDTV signal for selecting, as an input signal for a digital lowpassfilter 56, the imaginary output signal of the baseband response of theVSB synchrodyne circuitry 30. The response of lowpass filter 56 is adigital AFPC signal supplied as input signal to a digital-to-analogconverter (DAC) 57. The output signal from the DAC 57 is an analog AFPCsignal, which is subjected to further lowpass filtering in an analoglowpass filter 58, the response of which filter 58 is used forcontrolling the frequency and phase of the oscillations that the secondlocal oscillator 16 provides. Analog lowpass filtering is advantageousto use for realizing long-time-constant lowpass filtering because thereis reduced need for active devices as compared to digital lowpassfiltering. Since the shunt capacitor of a resistance-capacitance lowpassfilter section can be at the interface between a tuner 5 IC and the ICcontaining the digital synchrodyning circuitry, the analog lowpassfiltering can be done without any cost in IC pin-out. Doing some digitallowpass filtering is advantageous, however, since the digital lowpassfilter response can be subsampled to the DAC 57; the reduced speedrequirements on the digital-to-analog conversion reduces the cost of theDAC 57.

The multiplexer 55 responds to the pilot carrier presence detector 34indicating that a pilot carrier is not included in the currentlyreceived DTV signal for selecting the input signal for the digitallowpass filter 56 from the circuitry for processing a QAM DTV signal.FIG. 1 shows the product output signal of a digital multiplier 29 beingprovided for such selection. The digital multiplier 29 multipliestogether the real and imaginary output signals of the QAM synchrodynecircuitry 25 to generate an unfiltered digital AFPC signal. Thegeneration of the unfiltered digital AFPC signal is very similar to thatin the well-known Costas loop. In the Costas loop the AFPC signal isused to control the frequency and phase of the digital localoscillations used for synchrodyning received signals to baseband. TheFIG. 1 arrangement departs from this procedure, the AFPC signal beingused instead to control the frequency and phase of the analogoscillations generated by the second local oscillator 16. This regulatesthe frequency and phase of the final IF signal supplied to the ADC 22for digitization and for subsequent synchrodyning to baseband in thedigital regime. As is the case with the Costas loop, the multiplier 29is preferably of especial design in which the real signal is convertedto a ternary signal for multiplying the imaginary signal; thissimplifies the digital multiplier and improves the pull-incharacteristics of the AFPC loop.

The second intermediate-frequency amplifier 19, the third localoscillator 20 (except for its outboard crystal and other frequencyselection components), and the third mixer 21 are advantageouslyconstructed within the confines of a monolithic IC; since the outputsignal of the third mixer 21 is at a different frequency than the inputsignal to the second IF amplifier 19, the second IF amplifier 19 canhave high gain without attendant high risk of unwanted regeneration. Thefirst IF amplifier 14, the second local oscillator 16 (except for itsoutboard crystal and other frequency selection components) and thesecond mixer 17 can be constructed within the confines of the same IC,or they may be constructed otherwise—e.g., within other integratedcircuitry. The analog-to-digital converter (ADC), as customary, will bea flash type with at least ten bits resolution and is preferablyconstructed within the confines of a different monolithic IC than the IFamplifiers. The analog lowpass filter at the input of the converterisolates the sampling circuitry, with its associated switchingtransients, from the IC in which the high-gain second IF amplifier 19 islocated (and in some cases, in which the first IF amplifier 14 is alsolocated). This reduces the likelihood of unwanted regeneration in thetuner 5. Considerable die area is required for the resistance ladderused in establishing the quantizing levels and for the large number ofanalog comparators involved in an ADC of flash type, so often such anADC does not share a monolithic IC with other elements anyway.

The elements 23 - 35, 55 and 56 are advantageously constructed withinthe confines of a single monolithic integrated circuit (IC), to reducethe number of wiring connections made outside the confines of amonolithic IC. The synchrodyning circuits 25 and 30 both receive inputsignals from the real-to-complex sample converter 24, and portions oftheir respective address generators 28 and 32 can usually be provided bycircuitry shared in common. It is advantageous that this singlemonolithic IC and the circuitry that follows this IC include all thecircuitry for automatically selecting the appropriate mode of receptionfor the DTV transmission currently being received. Such practice avoidsthe need for operating the third local oscillator at two markedlydifferent frequencies, depending on whether a DTV signal is of QAM typeor is of VSB type. Operation of the third local oscillator at twomarkedly different frequencies is normally associated with the use oftwo different crystals for setting those frequencies. Operating thethird local oscillator at essentially the same frequency, no matterwhether the DTV signal is of QAM type or is of VSB type, saves the costof the extra crystal and of the electronic switching circuitry involvedwith the use of two crystals. Furthermore, the reliability of the tuner5 is improved by the reduction in the amount of circuitry locatedoutside the monolithic integrated circuitry.

If the ADC is not constructed within an IC, all or substantially all itsown, it is advantageous to include it in the IC that contains thecircuitry for synchrodyning VSB DTV signals and the circuitry forsynchrodyning QAM DTV signals to baseband, since the signals forclocking the sampling of the final IF signal by the ADC are to begenerated within that IC. Furthermore, the analog lowpass filter at theinput of the converter still isolates the sampling circuitry, with itsassociated switching transients, from the IC(s) in which high-gain IFamplification is done.

FIG. 3 shows in more detail the digital circuitry 25 for synchrodyningQAM DTV signals to baseband. The QAM synchrodyning circuitry 25 includesthe QAM in-phase synchronous detector 250 for generating the realportion of its output signal and the QAM quadrature-phase synchronousdetector 255 for generating the imaginary portion of its output signal.The QAM synchrodyning circuitry 25 includes a digital adder 256, adigital subtractor 257, and respective first, second, third and fourthdigital multipliers 251-254. The QAM in-phase synchronous detector 250includes the multiplier 251, the multiplier 252, and the adder 256 foradding the product output signals of the multipliers 251 and 252 togenerate the real portion of the output signal of the QAM synchrodyningcircuitry 25. The first digital multiplier 251 multiplies the realdigital samples of final IF signal supplied from thereal-to-complex-sample converter 24 by digital samples descriptive ofthe cosine of the QAM carrier that are read from the look-up table 271in the ROM 27, and the second digital multiplier 252 multiplies theimaginary digital samples of final IF signal supplied from thereal-to-complex-sample converter 24 by digital samples descriptive ofthe sine of the QAM carrier that are read from the look-up table 272 inthe ROM 27. The QAM quadrature-phase synchronous detector 255 includesthe multiplier 253, the multiplier 254, and the subtractor 257 forsubtracting the product output signal of the multiplier 253 from theproduct output signal of the multiplier 254 to generate the imaginaryportion of the output signal of the QAM synchrodyning circuitry 25. Thethird digital multiplier 253 multiplies the real digital samples offinal IF signal supplied from the real-to-complex-sample converter 24 bydigital samples descriptive of the sine of the QAM carrier that are readfrom the look-up table 272 in the ROM 27, and the fourth digitalmultiplier 254 multiplies the imaginary digital samples of final IFsignal supplied from the real-to-complex-sample converter 24 by digitalsamples descriptive of the cosine of the QAM carrier that are read fromthe look-up table 271 in the ROM 27.

FIG. 3 also shows in more detail the digital circuitry 30 forsynchrodyning VSB DTV signals to baseband. The VSB synchrodyningcircuitry 30 includes the VSB in-phase synchronous detector 300 forgenerating the real portion of its output signal and the VSBquadrature-phase synchronous detector 305 for generating the imaginaryportion of its output signal. The VSB synchrodyning circuitry 30includes a digital adder 306, a digital subtractor 307, and respectivefirst, second, third and fourth digital multipliers 301-304. The VSBin-phase synchronous detector 300 includes the multiplier 301, themultiplier 302, and the adder 306 for adding the product output signalsof the multipliers 301 and 302 to generate the real portion of theoutput signal of the VSB synchrodyning circuitry 30. The first digitalmultiplier 301 multiplies the real digital samples of final IF signalsupplied from the real-to-complex-sample converter 24 by digital samplesdescriptive of the cosine of the VSB carrier that are read from thelook-up table 311 in the ROM 31, and the second digital multiplier 302multiplies the imaginary digital samples of final IF signal suppliedfrom the real-to-complex-sample converter 24 by digital samplesdescriptive of the sine of the VSB carrier that are read from thelook-up table 312 in the ROM 31. The VSB quadrature-phase synchronousdetector 305 includes the multiplier 303, the multiplier 304, and thesubtractor 307 for subtracting the product output signal of themultiplier 303 from the product output signal of the multiplier 304 togenerate the imaginary portion of the output signal of the VSBsynchrodyning circuitry 30. The third digital multiplier 303 multipliesthe real digital samples of final IF signal supplied from thereal-to-complex-sample converter 24 by digital samples descriptive ofthe sine of the VSB carrier that are read from the look-up table 312 inthe ROM 31, and the fourth digital multiplier 304 multiplies theimaginary digital samples of final IF signal supplied from thereal-to-complex-sample converter 24 by digital samples descriptive ofthe cosine of the VSB carrier that are read from the look-up table 311in the ROM 31.

FIG. 4 shows in detail a representative construction of the sample clockgenerator 23. This construction includes a voltage-controlled oscillator230 that generates cissoidal oscillations nominally of 21.52 MHzfrequency. The oscillator 230 is a controlled oscillator, the frequencyand phase of its oscillations being controlled by an automatic frequencyand phase control (AFPC) signal voltage. This AFPC signal voltage isgenerated by an automatic frequency and phase control (AFPC) detector231, which compares frequency-divided response to the oscillations ofthe oscillator 230 with a 10.76 MHz reference carrier supplied from adigital-to-analog converter (DAC) 232. Preferably, oscillator 230 is ofa type using a crystal for stabilizing the natural frequency and phaseof its oscillations. A symmetrical clipper or limiter 233 generates anessentially squarewave response to these cissoidal oscillations, whichis used as the first clock signal for timing the sampling of the finalIF signal in the ADC 22. A frequency-divider flip-flop 234 responds totransitions of the first clock signal in a prescribed sense forgenerating another square wave with a fundamental frequency of 10.76MHz, half the frequency of the oscillations of the oscillator 230. Thisfrequency-divided response to the oscillations of the oscillator 230 issupplied to the AFPC detector 231 for comparison with the 10.76 MHzreference carrier supplied from the DAC 232. The frequency-dividerflip-flop 234 also supplies squarewave output signal with a fundamentalfrequency of 10.76 MHz to an AND circuit 235 to be ANDed with the firstclock signal for generating a second clock signal used by the 2:1decimator 35 shown in FIG. 1.

The 21.52 MHz reference carrier supplied from the digital-to-analogconverter 232 is generated by extracting a component of the received DTVsignal as synchrodyned to baseband, which component is of a frequencythat is a subharmonic of the symbol frequency (or baud frequency), andmultiplying that subharmonic of the symbol frequency by an appropriatefactor in frequency multiplier circuitry. As evidenced by the article“Understanding Timing Recovery and Jitter in Digital TransmissionSystems—Part 1” by Kenneth J. Bures published in the October 1992 issueof RF Design, there was knowledge in the prior art that it is possiblein the analog regime to recover symbol timing information from certaintypes of symbol code in which the baud frequency is absent, bysubjecting the symbol code to narrow bandpass filtering centered on asubharmonic of the baud frequency followed by squaring or othernon-linear procedure that will generate harmonics from which the baudfrequency may be extracted by frequency-selective filtering. The narrowbandpass filters used for lower symbol code rates include LC filters andphase-locked loops (PLLs), while SAW filters are preferred for highersymbol code rates. What is unusual about the symbol recovery procedurein the sample clock generator 23 shown in FIGS. 4 and 5 is that thismethod for recovering symbol timing information that is generally knownis modified for use in the digital regime, using afinite-impulse-response digital bandpass filter having its elementsclocked by the sample clock generator itself for selecting a prescribedsubmultiple of the symbol frequency in the digitized symbol codestream.Prospectively considered there was no assurance that this modifiedmethod would in fact work, since the effects of the digital samplingprocess are difficult to evaluate, particularly when the sampling rateis itself subject to control by the result of the modified method.

The modified method does work, however, as long as the frequencies usedfor generating AFPC error signal fall within the passbands of bandpassFIR digital filters which center on submultiples of the VCO 230oscillation frequency, so that the AFPC loop can pull the VCO 230 intofrequency and phase lock. In fact, the modified method is advantageousin that the bandpass FIR digital filters perform as tracking filters,being clocked by the sample clock generator. After frequency and phaselock of the VCO 230, there are no phase shift effects caused by thesymbol rate subharmonics and harmonics not falling exactly at the centerfrequencies of the bandpass filters. The modified method will now bespecifically described, first presuming the received DTV signal is a VSBsignal with a 10.76 MHz symbol frequency, and then presuming thereceived DTV signal is a QAM signal with a 5.38 MHz symbol frequency.

A digital multiplexer 236 responds to the pilot carrier presencedetector 34 detecting pilot carrier accompanying the received DTVsignal, which is indicative that the received DTV signal is a VSBsignal, to select the real samples of this signal supplied from a VSBin-phase synchronous detector 300 for application to a bandpass FIRdigital filter 237 that provides a selective response centered at 5.38MHz, which selects the first subharmonic of symbol frequency from theVSB signal. The filter 237 response is squared by a squaring circuit238, which generates harmonics of the filter 237 response including astrong 10.76 MHz component as second harmonic of 5.38 MHz. A bandpassFIR digital filter 239 that provides a selective response centered at10.76 MHz selects this second harmonic for application to the DAC 232 asits digital input signal descriptive of its 10.76 MHz reference carrieranalog output signal.

The digital multiplexer 236 responds to the pilot carrier presencedetector 34 not detecting pilot carrier accompanying the received DTVsignal, which is indicative that the received DTV signal is a QAMsignal, to select the output signal of a squaring circuit 23A forapplication to the bandpass filter 237 that provides a selectiveresponse centered at 5.38 MHz. A bandpass FIR digital filter 23B thatprovides a selective response centered at 2.69 MHz for selecting the2.69 MHz first subharmonic of the symbol frequency of a baseband QAMsignal supplies input signal to the squaring circuit 23A, whichgenerates harmonics of the filter 23B response including a strong 5.38MHz component. This baseband QAM signal can be supplied either from theQAM in-phase synchronous detector 250, as shown in FIG. 4, or from theQAM quadrature-phase synchronous detector 255.

The squaring circuit 238 is shown in FIG. 4 as a digital multiplierreceiving the filter 237 response both as multiplier and multiplicand;and the squaring circuit 23A is shown as a digital multiplier receivingthe filter 23B response both as multiplier and multiplicand. Each of thesquaring circuits 238 and 23A can be constructed from logic gates as adigital multiplier, but for the sake of speedier operation is betterprovided by a ROM storing a look-up table of squares. An absolute-valuecircuit can be used as a substitute for the squaring circuit ingenerating harmonics of the response of a preceding filter, but producesweaker second harmonics and so is not preferred.

FIG. 4 also shows in more detail a representative construction of thefirst address generator 28, which supplies addresses to a cosine look-uptable portion 271 and a sine look-up table portion 272 of the ROM 27that provides complex-number digital descriptions of two phasings of theQAM carrier, as translated to a final intermediate frequency and inquadrature relationship with each other. Transitions of the first clocksignal are counted by a first address counter 281 in the first addressgenerator 28 to generate a basic first address signal. This basic firstaddress signal is applied as a first summand to a digital adder 282. Afirst address correction signal, which is applied to the adder 282 as asecond summand, adds to the basic first address signal in the adder 282for generating as a sum output signal a corrected first address signalfor addressing both the cosine look-up table portion 271 and the sinelook-up table portion 272 of the ROM 27. A symbol-clock-rotationdetector 283 responds to the sequence of real samples of QAM signal assynchrodyned to baseband by the QAM in-phase synchronous detector 250and to the sequence of imaginary samples of QAM signal as synchrodynedto baseband by the QAM quadrature-phase synchronous detector 255. Thesymbol-clock-rotation detector 283 detects the misphasing between symbolclocking done at the receiver in accordance with the first clock signaland symbol clocking done at the transmitter, as evidenced in thereceived QAM signal heterodyned to a final intermediate frequency thatis a submultiple of its symbol frequency. Several types ofsymbol-clock-rotation detector 283 are described and backgroundliterature describing certain of them are catalogued in U.S. Pat. No.5,115,454 issued May 19, 1992 to A. D. Kucar, entitled METHOD ANDAPPARATUS FOR CARRIER SYNCHRONIZATION AND DATA DETECTION, andincorporated herein by reference. A digital lowpass filter 284 averagesover many samples (e. g., several million) the misphasing of the symbolclocking done at the receiver as detected by the symbol-clock-rotationdetector 283 to generate the first address correction signal supplied tothe adder 282 to correct the basic first address. Averaging over so manysamples can be done by procedures which accumulate lesser numbers ofsamples and dump them forward at a reduced sample few times withprogressively lower subsampling rates. few times with progressivelylower subsampling rates.

FIG. 4 also shows in more detail a representative construction of thesecond address generator 32, which supplies addresses to a cosinelook-up table portion 311 and a sine look-up table portion 312 of theROM 31 that provides complex-number digital descriptions of two phasingsof the VSB carrier, as translated to a final intermediate frequency andin quadrature relationship with each other. Transitions of the firstclock signal are counted by a second address counter 321 in the secondaddress generator 32 to generate a basic second address signal. Thisbasic second address signal is applied as a first summand to a digitaladder 322. A second address correction signal, which is applied to theadder 322 as a second summand, adds to the basic second address signalin the adder 322 for generating as a sum output signal a correctedsecond address signal for addressing both the cosine look-up tableportion 311 and the sine look-up table portion 312 of the ROM 31.

FIG. 4 shows a clocked digital delay line 323 for delaying the samplesfrom the in-phase synchronous detector 300 by a prescribed number ofsample periods prior to their being applied as input signal to aquantizer 324, which supplies the quantization level most closelyapproximated by the sample currently received by the quantizer 324 asinput signal. The quantization levels can be inferred from the energy ofthe pilot carrier accompanying the VSB signal or can be inferred fromthe result of envelope detection of the VSB signal. The closestquantization level selected by the quantizer 324 as its output signalhas the corresponding quantizer 324 input signal subtracted therefrom bya digital adder/subtractor 325, which is operated as a clocked elementby including a clocked latch at its output. The difference output signalfrom the adder/ subtractor 325 describes the departure of the symbollevels actually recovered from those that should be recovered, butwhether the polarity of the departure is attributable to symbolmisphasing being leading or lagging remains to be resolved. The samplesfrom the in-phase synchronous detector 300 applied as input signal tothe clocked digital delay line 323 are applied without delay as inputsignal to a mean-square-error gradient detection filter 326. The filter326 is a finite-impulse-response (FIR) digital filter having a (−½), 1,0, (−1), (+½) kernel, the operation of which is clocked by the firstsampling clock. The prescribed number of sample periods of delayprovided by the clocked digital delay line 323 is such that filter 326response is in temporal alignment with the difference signal from theadder/subtractor 325. A digital multiplier 327 multiplies the differencesignal from the adder/subtractor 325 with the filter 326 response toresolve this issue. The sign bit and the next most significant bit ofthe two's complement filter 326 response suffice for the multiplication,which permits simplification of the digital multiplier 327 structure.The samples of the product signal from the digital multiplier 327 areindications of the misphasing of the symbol clocking done at thereceiver that are averaged over many samples (e. g., several million) bya digital lowpass filter 328 for generating the second addresscorrection signal supplied to the adder 322 to correct the basic secondaddress.

The symbol synchronization techniques used in the second addressgenerator 32 shown FIG. 4 are of the same general type as S. U. H.Qureshi describes for use with pulse amplitude modulation (PAM) signalsin his paper “Timing Recovery for Equalized Partial-Response Systems,IEEE Transactions on Communications”, Dec. 1976, pp. 1326-1330. Thesesymbol synchronization techniques as used in connection with symbolsynchronization for VSB signals are specifically described by theinventors in their earlier-filed applications referenced earlier in thisspecification. In preferred designs of the general type of secondaddress generator 32 shown in FIGS. 4 and 5, the clocked digital delayline 323 does not exist as a separate element; instead, an input signalto the quantizer 324 with the requisite number of sample periods ofdelay for the difference signal from the adder/subtractor 325 beingtemporally aligned with the filter 326 response is taken from the tappeddigital delay line included in the filter 326 for supplyingdifferentially delayed samples to be weighted by the (−½), 1, 0, (−1),(+½) kernel before being summed to generate the filter 326 response.

The carrier of a QAM DTV signal and the carrier of a VSB DTV signal aretranslated to respective final intermediate frequencies that areseparated 2.69 MHz from each other, since the carrier of the QAM DTVsignal is at the center of a 6-MHz-wide TV channel, but the carrier ofthe VSB DTV signal is only 310 kHz above the lowest frequency of a6-MHz-wide TV channel. The frequencies of the local oscillators 11, 16and 20 in the tuner 5 of FIG. 1 can be chosen so that the intermediatefrequency to which the carrier of a VSB DTV signal is translated ishigher than that to which the carrier of a QAM DTV signal is translated,with the vestigial and full sidebands of the VSB DTV signal beingrespectively above and below its carrier. Alternatively, the frequenciesof the local oscillators 11, 16 and 20 can be chosen so that theintermediate frequency to which the carrier of a VSB DTV signal istranslated is lower than that to which the carrier of a QAM DTV signalis translated, with the vestigial and full sidebands of the VSB DTVsignal being respectively below and above its carrier.

Preferably the lowest frequency of the final IF signal is above 1 MHz,to keep the ratio of the highest frequency of the final IF signalthereto substantially below 8:1 and thereby ease the filteringrequirements for the real-to-complex-sample converter 24. To satisfythis preference in regard to the QAM signal alone, the lowest carrierfrequency for the QAM carrier in the final IF signal is 3.69 MHz. Tosatisfy this preference in regard to the VSB signal alone, the lowestthe carrier frequency for the VSB carrier in the final IF signal couldbe is 1.31 MHz, presuming its full sideband to be above its vestigialsideband in frequency, or 6.38 MHz, presuming its full sideband to bebelow its vestigial sideband in frequency. Presuming the full sidebandof the VSB signal to be above its vestigial sideband in frequency, sincethe carrier frequency of the VSB carrier most be at least 1.31 MHz, thecarrier frequency of the QAM carrier must be at least 4.00 MHz.Presuming the full sideband of the VSB signal to be below its vestigialsideband in frequency, since the carrier frequency of the VSB carriermost be at least 6.38 MHz, the carrier frequency of the QAM carrier muststill be at least 3.69 MHz.

If the sample rate in the ADC 22 is established by the first clocksignal from the sample clock generator 23 to be 21.52 * 10⁶ samples persecond, preferably the intermediate frequency to which the carrier of aQAM DTV signal is translated is not higher than 5.38 MHz, so that it canbe sampled at least four times per cycle. Presuming the full sideband ofthe VSB signal to be above its vestigial sideband in frequency, thispreference constrains the lowest frequency in the final IF signal tobeing no higher than 2.38 MHz and the carrier of the VSB signal being nohigher than 2.69 MHz. FIG. 11 illustrates how, for these presumedconditions, the VSB carrier is constrained to the band 1.31-2.69 MHz,and the QAM carrier is constrained to the band 4.00-5.38 MHz.

Presuming the full sideband of the VSB signal to be below its vestigialsideband in frequency, the QAM carrier is constrained to the band3.69-5,38 MHz. Accordingly, the carrier of the VSB signal is constrainedto the band 6.38-8.07 MHz in order that the 2.69 MHz offset betweencarriers is maintained. FIG. 12 illustrates the case where the QAMcarrier is constrained to the band 3.69-5.38 MHz and the VSB carrier isconstrained to the band 6.38-8.07 MHz.

The final intermediate frequency to which the QAM carrier is translatedmust be a submultiple of a multiple of the 21.52 MHz sampling rate inorder that this carrier can be described on a continuous basis relyingon a sine-cosine look-up table in the ROM 27. The final intermediatefrequency to which the VSB carrier is translated must be a submultipleof a multiple of the 21.52 * 10⁶ samples-per-second sampling rate inorder that this carrier can be described on a continuous basis relyingon a sine-cosine look-up table in the ROM 31. The final intermediatefrequency (m/n) times the 21.52 MHz sampling rate, to which the carrieris translated, preferably has a small value of n, to keep the number ofvalues in the sine-cosine look-up tables stored in ROM reasonably small.(Note that the variables m and n referred to here have no relationshipto the variables M and N referred to in the SUMMARY OF INVENTION.)

One can search for respective intermediate frequencies to which thecarrier of a QAM DTV signal and the carrier of a VSB DTV signal are tobe translated, which frequencies meet the criteria set forth above, byfollowing procedure taught in U.S. Pat. No. 5,506,636. A table ofsubharmonics of successive harmonics of the 10.76 MHz VSB symbol rate,which the sampling clock rate is harmonically related to, is constructedfor the frequency ranges of interest. Then pairs of subharmonics of thesame harmonic which exhibit the desired 2.69 MHz difference in frequencybetween them are considered with regard to their relative advantages ascarriers.

The third and seventh subharmonics of 21.52 MHz at 5.38 MHz and at 2.39MHz exhibit substantially the desired 2.69 MHz offset and areappropriate for use as QAM carrier and a VSB carrier with its fullsideband above its vestigial sideband in frequency. The 2.69 MHz offsetbetween these subharmonics is one-quarter the symbol rate of10,762237.762 samples per second, or 2,690559.4 Hz, rather than the2,690,122.4 Hz offset between the QAM and VSB carriers required tooffset the VSB carrier from a co-channel interfering NTSC video carrierby 59.75 times the nominal NTSC horizontal scanning frequency. Thissmall 437 Hz frequency discrepancy is easily accommodated by theautomatic frequency and phase control of the controlled local oscillator16 in the tuner 5 of FIG. 1. The addressing of ROMs 27 and 31 is greatlysimplified when the QAM and VSB carriers are translated to be close tothe third and seventh subharmonics of 21.52 MHz in final IF signals,since advantage can be taken of repetitive symmetries in the stored sineand cosine functions, to reduce the number of bits in the addressesapplied to ROM.

The second harmonic of the 21.52 MHz sampling frequency is 43.05 MHz,and its subharmonics can be searched, looking for a pair offset fromeach other in frequency by an amount substantially equal to 2.69 MHz.The seventh and fifteenth subharmonics of 43.05 MHz are the third andseventh subharmonics of 21.52 MHz which have already been considered.The ninth and twenty-sixth subharmonics of 43.05 MHz at 4.305 MHz and at1.594 MHz exhibit a 20 kHz or 0.74% error in regard to the desired 2.69MHz offset and could respectively serve as QAM carrier and as VSBcarrier. This error is within the 30 kHz or so mistuning tolerated inpast commercial designs for NTSC TV receivers. The ROM 31 storingsine-cosine look-up tables for the twenty-sixth subharmonic of 43.05 MHzhas to store an excessive number of samples, however; and the ROM 27storing sine-cosine look-up tables for the ninth subharmonic of 43.05MHz has to store an appreciable number of samples, too.

The third harmonic of the 21.52 MHz sampling frequency is 64.57 MHz, andits subharmonics can be searched, looking for a subharmonic offset infrequency from a subharmonic of 43.05 MHz or from another subharmonic of64.57 MHz by an amount substantially equal to 2.69 MHz. The twelfthsubharmonic of 64.57 MHz, 4.967 MHz, and the eighteenth subharmonic of43.05 MHz, 2.265 MHz, exhibit a 12 kHz or 0.45% error in regard to thedesired 2.69 MHz offset and could respectively serve as QAM carrier andas a VSB carrier with its full sideband above its vestigial sideband infrequency. This error is well within the 30 kHz or so of mistuningtolerated in past commercial designs for NTSC TV receivers. However, theROM 27 storing sine-cosine look-up tables for the twelfth subharmonic of64.57 MHz has to store an excessive number of samples; and the ROM 31storing sine-cosine look-up tables for the eighteenth subharmonic of43.05 MHz has to store an excessive number of samples, too.

The seventh subharmonic of 64.57 MHz is 8.07 MHz, offset almost exactlythe desired 2.69 MHz from the third subharmonic of 21.52 MHz. This thirdsubharmonic of 21.52 MHz, 5.38 MHz, and the seventh subharmonic of 64.57MHz, 8.07 MHz, are appropriate for use as QAM carrier and a VSB carrierwith its full sideband below its vestigial sideband in frequency.

It appears preferable that the frequencies of the local oscillators 11,16 and 20 in the tuner 5 of FIG. 1 be chosen so that the intermediatefrequency to which the carrier of a QAM DTV signal is translated is 5.38MHz, the presumed symbol rate for the QAM DTV signal and half thestandard symbol rate for the VSB DTV signal. Accordingly, if the VSBcarrier is translated in frequency so as to have its full sideband aboveits vestigial sideband in frequency in the final IF signal, thepreferred frequency of the VSB carrier in the final IF signal is 2.69MHz. Alternatively, if the VSB carrier is translated in frequency so asto have its full sideband below its vestigial sideband in frequency inthe final IF signal, the preferred frequency of the VSB carrier in thefinal IF signal is 8.07 MHz.

It is noted in passing that all the subharmonics of 43.05 MHz and allthe subharmonics of 64.57 MHz are subharmonics of 129.15 MHz, the thirdharmonic of 43.05 MHz and the second harmonic of 64.57 MHz. The 2.69MHz, 5.68 MHz and 8.07 MHz frequencies are the forty-seventh,twenty-third and fifteenth subharmonics, respectively, of 129.15 MHz. Itis also noted that while the harmonic relationship between carriers havebeen considered in terms of harmonics of the 21.52 MHz sampling ratethat is the second harmonic of the 10.76 MHz VSB symbol rate, theconsideration thus far can be viewed as involving the even harmonics ofthe 10.76 MHz symbol rate. A more complete consideration of the possibleharmonic relationships between carriers also includes consideration ofodd harmonics, at least third, of the 10.76 MHz VSB symbol rate. The2.69 MHz, 5.68 MHz and 8.07 MHz frequencies are respectively theeleventh, fifth and third subharmonics of 32.29 MHz, 32.29 MHz beingthree times the 10.76 MHz symbol rate of the VSB signal.

One skilled in the art of designing analog-to-digital conversioncircuitry for digital systems will appreciate that the sampling ofanalog signals for digitization can use various widths of samplingwindow. Thus far, it has been presumed that 21.52 * 10⁶ samples persecond are taken with the duration of each sampling window extendingover half a cycle of 21.52 MHz. The pulses from the limiter 233 can bestretched to nearly twice this duration, if desired. Another alternativethat is possible is to design the analog-to-digital converter to use twostaggered sets of sampling windows with each sampling window extendingover half a cycle of 21.52 MHz to digitize on a staggered-phase basis ata 43.05 * 10⁶ samples per second combined rate. The digitization offinal IF signal at a 43.05 MHz * 10 ⁶ samples per second improvesautomatic phase and frequency control accuracy.

FIG. 5 shows a modification of the FIG. 4 circuitry that is possiblewhen the third and the seventh subharmonics of 21.52 MHz are used as thefinal intermediate frequencies to which the QAM and VSB DTV carriers arerespectively converted. In a modification 320 of the second addressgenerator 32 described above, second address counter 321 is arranged tocount modulo eight when sampling rate is 21.52 * 10⁶ samples per second,thereby to generate two cycles of ROM 27 addressing and the one cycle ofaddressing for a ROM 310 that replaces the ROM 31; and the lesssignificant bits of the output count from the second address counter 321are made available for replacing the basic first address from the firstaddress counter 281. In a modification 280 of the first addressgenerator 28 described above, the first address counter 281 is dispensedwith, and the less significant bits of the second address counter 321are applied to the adder 282 as basic first address instead of the countfrom the first address counter 281. The VSB complex carrier ROM 31 isreplaced with a ROM 310 that comprises a portion 313 that stores onlyone-half cycle of VSB carrier cosine values and a portion 314 thatstores only one-half cycle of VSB carrier sine values. These portions313 and 314 of the ROM 310 are addressed by the less significant bits ofthe adder 322 sum output signal. A selective bits complementor 315exclusive-ORs the most significant bit of the adder 322 sum outputsignal with each of the bits of the VSB carrier cosine values read fromthe portion 313 of the ROM 310 for generating a first summand input fora digital adder 317, and the most significant bit of the adder 322 sumoutput signal is provided with zero extension in the direction ofincreased significance for generating a second summand input for theadder 317. The sum output from the adder 317 provides eight cosinevalues of VSB carrier over eight first clock periods to define acomplete cycle of VSB carrier. A selective bits complementor 316exclusive-ORs the most significant bit of the adder 322 sum outputsignal with each of the bits of the VSB carrier sine values read fromthe portion 314 of the ROM 310 for generating a first summand input fora digital adder 318, and the most significant bit of the adder 322 sumoutput signal with zero extension in the direction of increasedsignificance is also applied as a second summand input for the adder318. The sum output from the adder 318 provides eight sine values of VSBcarrier over eight first clock periods to define a complete cycle of VSBcarrier.

The FIG. 5 or the FIG. 4 circuitry can also be used when the fifth andthird subharmonics of 32.29 MHz are used as the final intermediatefrequencies to which the QAM and VSB DTV carriers are respectivelyconverted. The contents of the portions 313 and 314 of the ROM 310 aremodified for the higher-frequency 8.07 MHz VSB carrier, of course.

One skilled in the art of digital circuit design will understand thatother hardware savings can be made in the FIG. 4 read-only memorycircuitry taking advantage of symmetries in the cosine and sinefunctions or the 90° offset in the respective phases of these twofunctions. One skilled in the art of digital circuit design andacquainted with the foregoing description will understand thatmodifications of the FIG. 4 and FIG. 5 circuitry are possible that havean AFPC detector for the VCO 230 in which the oscillations from the VCO230 as converted to square waves by the symmetrical clipper 233 arecompared in frequency with frequency doubler response to the 10.76 MHzsignal selected by the digital bandpass filter 237.

One skilled in the art of digital circuit design will be enabled byacquaintance with the foregoing description to implement circuitry inwhich the ADC 22 samples at a 43.05 * 10⁶ samples per second sample rateduring digitization. The VCO 230 is replaced by a VCO supplying 43.05MHz oscillations; and, by way of example, oscillations from the VCO 230as converted to square waves by the symmetrical clipper 233 andfrequency divided by the flip-flop 234 are compared in frequency withfrequency doubler response to the 10.76 MHz signal selected by thedigital bandpass filter 237. The 2:1 decimator 35 can be replaced by a4:1 decimator, and the squarewave output signal from the flip-flop 234can be divided by another factor of two by a further flip-flop toprovide support for generating a reduced-rate sample clock signal forthe 4:1 decimator.

FIG. 6 shows a form that the circuitry 24 can take, which comprises:

(a) a linear-phase, finite-impulse-response (FIR) digital filter 60 thatgenerates imaginary (Im) digital samples as a Hilbert transform responseto the real (Re) digital samples; and

(b) compensating, clocked digital delay of the real digital samples tocompensate for the latency time of the Hilbert transformation filter 60,which clocked digital delay can be provided by clocked latch elements61-66 included in the Hilbert transformation filter 60.

The use of such circuitry for implementing in-phase and quadrature-phasesampling procedures on bandpass signals is described by D. W. Rice andK. H. Wu in their article “Quadrature Sampling with High Dynamic Range”on pp. 736-739 of IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS,Vol. AES-18, No. 4 (Nov 1982). Since the frequency band 6 MHz wideoccupied by the final IF signal has a lowest frequency of at least amegaHertz or so, it is possible to use as few as seven non-zero-weightedtaps in the FIR filter 60 used for Hilbert transformation.

The seven-tap Hilbert transformation filter 60 includes a cascadeconnection of one-sample delay elements 61, 62, 63, 64, 65 and 66 fromwhich samples taken to be weighted and summed to generate the Hilberttransform response. The Hilbert transform is linear phase in nature sothe tap weights of the FIR filter 60 exhibit symmetry about mediandelay. Accordingly, a digital adder 67 sums the input signal to delayelement 61 and the output signal from the delay element 66 to beweighted in common, a digital adder 68 sums the output signal from thedelay element 61 and the output signal from the delay element 65 to beweighted in common, and a digital adder 69 sums the output signal fromthe delay element 62 and the output signal from the delay element 64 tobe weighted in common. The output signal from the delay element 64 isapplied as input address to a read-only memory 70, which multiplies thatsignal by an appropriate weight W₀ magnitude. The sum output signal fromthe digital adder 69 is applied as input address to a read-only memory71, which multiplies that signal by an appropriate weight W₁ magnitude.The sum output signal from the digital adder 68 is applied as inputaddress to a read-only memory 72, which multiplies that signal by anappropriate weight W₂ magnitude. The sum output signal from the digitaladder 67 is applied as input address to a read-only memory 73, whichmultiplies that signal by an appropriate weight W₃ magnitude. The use ofthe ROMs 70, 71, 72 and 73 as fixed-multiplicand multipliers keeps thedelay associated with multiplication negligibly short. The outputsignals of the ROMs 70, 71, 72 and 73 are combined by a tree of signeddigital adders 74, 75 and 76 operated as adders or subtractors, asrequired to appropriately assign signs to the magnitudes of the weightsW₀, W₁, W₂ and W₃ stored in the ROMs 70, 71, 72 and 73. The adders 67,68, 69, 74, 75 and 76 are assumed to be clocked adders each exhibitingone-sample latency, which results in the seven-tap FIR filter 60exhibiting a six-sample latency. Delay of the filter 60 input signalthat compensates for this latency is provided by the cascade connectionof the six one-sample delay elements 61, 62, 63, 64, 65 and 66. Theinput address to the read-only memory 70 is taken from the output of thedelay element 64, rather than from the output of the delay element 63,so the one-sample delay of delay element 64 compensates for theone-sample delays in the adders 67, 68 and 69.

C. M. Rader in his article “A Simple Method for Sampling In-Phase andQuadrature Components”, IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONICSYSTEMS, Vol. AES-20, No. 6 (Nov 1984), pp. 821-824, describesimprovements in complex synchronous detection carried out on digitizedbandpass signals. Rader replaces the Hilbert-transform FIR filter andthe compensating-delay FIR filter of Rice and Wu with a pair of all-passdigital filters designed based on Jacobian elliptic functions andexhibiting a constant π/2 difference in phase response for the digitizedbandpass signals. A preferred pair of such all-pass digital filters,which are of infinite-impulse-response (IIR) type, has the followingsystem functions:

H₁(z)=z⁻¹(z⁻²-a²)/(1−a²z⁻²)a²=0.5846832

H₂(z)=—(z⁻²-b²)/(1−b²z⁻²)b²=0.1380250

Rader describes filter configurations which require only twomultiplications, one by a² and one by b².

FIG. 7 shows an alternative form that the circuitry 24 can take, whichcomprises a pair of all-pass digital filters 80 and 90 of a typedescribed by C. M. Rader and designed based on Jacobian ellipticfunctions. The filters 80 and 90 exhibit a constant π/2 difference inphase response for digitized bandpass signals. Since oversampled realsamples better provide for symbol synchronization when synchrodyning VSBsignals, the inventors prefer not to use the all-pass filters alsodescribed by Rader that exploit sub-sampling to provide furtherreductions in the delay network circuitry.

The construction of the filter 80, which provides the system functionH₁(z)=z⁻¹(z⁻²-a²)/(1−a² z⁻²), where a²=0.5846832 in decimal arthmetic,is shown in FIG. 7 to be as follows. The samples from the ADC 22 aredelayed by one ADC sample clock duration in a clocked delay element 88for application to a node 89. The signal at node 89 is further delayedby two ADC sample clock durations in cascaded clocked delay elements 81and 82, for application as first summand signal to a digital adder 83.The sum output signal of the adder 83 provides the real response fromthe filter 80. The sum output signal of the adder 83 is delayed by twoADC sample clock durations in cascaded clocked delay elements 84 and 85,for application as minuend input signal to a digital subtractor 86 thatreceives the signal at node 89 as its subtrahend input signal. Theresulting difference output signal from the digital subtractor 86 issupplied as multiplier input signal to a digital multiplier 87 formultiplying an a² multiplicand signal, using a binary arithmetic. Theresulting product output signal is applied to the digital adder 83 asits second summand signal.

The construction of the filter 90, which provides the system function-H₂(z)=(z⁻²-b²)/(1−b²z⁻²), where b²=0.1380250 in decimal arithmetic, isshown in FIG. 7 to be as follows. The samples from the ADC 22 aredelayed by two ADC sample clock durations in cascaded clocked delayelements 91 and 92, for application as first summand signal to a digitaladder 93. The sum output signal of the adder 93 provides the imaginaryresponse from the filter 90. The sum output signal of the adder 93 isdelayed by two ADC sample clock durations in cascaded clocked delayelements 94 and 95, for application to a digital subtractor 96 as itsminuend signal. The subtractor 96 receives the samples from the ADC 22as its subtrahend input signal. The resulting difference output signalfrom the digital subtractor 96 is supplied as multiplier input signal toa digital multiplier 97 for multiplying a b² multiplicand signal, usinga binary arithmetic. The resulting product output signal is applied tothe digital adder 93 as its second summand signal.

FIG. 8 shows a complex-signal filter resulting from modifying the FIG. 7complex-signal filter as follows. The position of the clocked delayelement 88 is shifted so as to delay the sum output signal of the adder83, rather than to delay the digital output signal of the ADC 22, andthe digital output signal of the ADC 22 is applied to the node 89without delay, thereby to cause real response to be provided at theoutput port of the shifted-in-position clocked delay element 88. Thereal response provided at the output port of the shifted-in -positionclocked delay element 81 is the same as the response provided at theoutput port of the clocked delay element 84. So, the real response isprovided from the output port of the clocked delay element 84 instead offrom the output port of the shifted-in-position clocked delay element81; and the shifted-in-position clocked delay element 81, being nolonger required, is dispensed with.

FIG. 9 shows a complex-signal filter resulting from modifying the FIG. 8complex-signal filter as follows. The first summand signal for the adder83 is then taken from the cascaded clocked delay elements 91 and 92,rather than from the cascaded clocked delay elements 81 and 82. Thecascaded clocked delay elements 81 and 82, being no longer required, aredispensed with. The FIG. 9 complex-signal filter is preferred over thecomplex-signal filters of FIG. 7 and 8 in that redundant clocked delayelements are eliminated.

FIG. 10 is a detailed block schematic diagram of a complex-signal filterdeveloping a constant π/2 difference in phase between a real response Reand an imaginary response Im to the digitized bandpass signals, that issimilar the complex-signal filter described by T. F. S. Ng in UnitedKingdom patent application 2 244 410 A published Nov. 27, 1991 andentitled QUADRATURE DEMODULATOR. The Ng filters arefinite-impulse-response (FIR) digital filters, rather than IIR filtersas described by Rader. The FIG. 10 complex-signal filter differs fromthe filters described by Ng in that 2:1 decimation is done followingfiltering, rather than before.

This permits the real and imaginary filtering to be supported by ashared tapped delay line. FIG. 10 shows this shared tapped delay linecomposed of cascaded single-clock-delay elements 100-114, such aslatches that like the ADC 22 are clocked at four times symboltransmission rate. The single-clock-delay element 100 may be dispensedwith or subsumed into the ADC 22 in some designs. Digital adders andsubtractors in the FIG. 6 complex filter are assumed to be clocked atfour times symbol transmission rate, with each having asingle-clock-duration latency. The digital multipliers are assumed to bea wired place shift in the case of a multiplication by an integral powerof two or to be provided from read-only memory (ROM), so there is zerolatency in each of the multiplications insofar as clocked operation isconcerned. At least the eight-bit resolution in the filter results perNg is presumed.

In order to generate the real response H₁(z), the real-response filteris presumed to apply tato apply tap weights W₀=4, W₁=0, W₂=−12, W₃=−72,W₄=72, W₅=12, W₆=0 and W₇=−4 per the example described by Ng, Thereal-response filter, in addition to the single-clock-delay elements100-114, includes a digital subtractor 121 for subtracting the responseof the delay element 114 from the response of the delay element 100, adigital multiplier 122 for weighting the differential response of thesubtractor 121 by a factor of four, a digital subtractor 125 forsubtracting the response of the delay element 103 from the response ofthe delay element 109, a digital multiplier 126 for weighting thedifferential response of the subtractor 125 by a factor of twelve, adigital subtractor 127 for subtracting the response of the delay element105 from the response of the delay element 107, a digital multiplier 128for weighting the differential response of the subtractor 127 by afactor of seventy-two, a digital adder 129 for summing the products fromthe digital multipliers 126 and 128, a digital adder 130 for summing theproduct from the digital multiplier 122 with the sum output signal fromthe adder 129, and a 2:1 decimator 131 for generating the real filterresponse Re in decimated response to the sum output signal from theadder 130.

The subtractor 121 subtracts the response of the delay element 114 fromthe response of the delay element 100, rather than subtracting theresponse of the delay element 113 from the output signal of the ADC 22,to introduce single-clock-duration delay to compensate for the latencyof the adder 129. Since W₁=0 and W₆=0, there is no digital subtractor123 for subtracting the response of the delay element 111 from theresponse of the delay element 101 or digital multiplier 124 forweighting the differential response of the subtractor 123. Consequently,there is no digital adder for summing product from the multiplier 124with the product from the multiplier 122. This gives rise to the need tocompensate for the latency of the adder 129.

In order to generate the imaginary response H₁(z), theimaginary-response filter is presumed to apply tap weights W₈=8, W₉=14,W₁₀=22, W₁₁=96, W₁₂=22, W₁₃=14, W₁₄=8 corrected from the exampledescribed by Ng. The imaginary-response filter, in addition to thesingle-clock-delay elements 100-112, includes a digital adder 141 foradding the response of the delay element 112 with the response of thedelay element 100, a digital multiplier 142 for weighting the sumresponse of the adder 141 by a factor of eight, a digital adder 143 foradding the response of the delay element 110 with the response of thedelay element 102, a digital multiplier 144 for weighting the sumresponse of the adder 143 by a factor of fourteen, a digital adder 145for adding the response of the delay element 108 with the response ofthe delay element 104, a digital multiplier 146 for weighting the sumresponse of the adder 145 by a factor of twenty-two, a digitalmultiplier 147 for weighting the response of the delay element 107 by afactor of ninety-six, a digital adder 148 for summing the products fromthe digital multipliers 142 and 144, a digital adder 149 for summing theproducts from the digital multipliers 146 and 147, a digital adder 150for summing the sum output signals from the adders 148 and 149, and a2:1 decimator 151 for generating the imaginary filter response Im indecimated response to the sum output signal from the adder 150.

The digital multiplier 147 weights the response of the delay element 107by a factor of ninety-six, rather than the response of the delay element106, in order to introduce single-clock-duration delay to compensate forthe single-clock-duration latency of each of the adders 141 143 and 145.

Less preferred embodiments of the invention are contemplated in whichthe trellis-decoded output signals of the two-dimensional symboldecoding circuitry 37 and of the one-dimensional symbol decodingcircuitry 38 are supplied to respective data de-interleavers, with datasource selection being deferred until data de-interleaving is completed.Other less preferred embodiments of the invention are contemplated inwhich embodiments the trellis-decoded output signal of thetwo-dimensional symbol decoding circuitry 37 is de-interleaved by arespective data de-interleaver and then decoded by a respectiveReed-Solomon decoder to generate a first stream of error-corrected data,in which embodiments the trellis-decoded output signal of theone-dimensional symbol decoding circuitry 38 is de-interleaved by arespective data de-interleaver and then decoded by a respectiveReed-Solomon decoder to generate a second stream of error-correcteddata, and in which embodiments data source selection is made between thefirst and second streams of error-corrected data. In modifications ofthese other less preferred embodiments of the invention the first andsecond streams of error-corrected data are supplied to separate datade-randomizers before data source selection is made. In other variantsseparate Reed-Solomon decoders are used for the QAM and VSB signals, butone data de-interleaver is used for both the QAM and VSB signals, or onedata de-randomizer is used for both the first and second streams oferror-corrected data.

The 2:1 decimator 35 of FIG. 1 is replaced by a 4:1 decimator inembodiments of the invention in which the ADC 22 samples at a 43.05 *10⁶ samples per second sample rate during digitization, rather than a21.52 * 10⁶ samples per second sample rate. Such change requiresappropriate modifications to the sample clock generator 23, of course. Asample rate higher than 21.52 * 10⁶ samples per second is used when thesynchrodyne circuitry 25 or 30 must synchrodyne to baseband a DTV signalhaving a carrier frequency higher than 5.38 MHz. Such a situationobtains when the synchrodyne circuitry 30 must synchrodyne to baseband aVSB signal having its vestigial sideband at frequencies greater thanthose in its full sideband. Decimators which decimate a baseband signalby a factor N at least two are better designed not to merely omitsamples but rather to pre-filter the baseband signal and then to omitsamples of the pre-filter response.

The preferred embodiments of the invention described supra use QAMsynchrodyning circuitry and VSB synchrodyning circuitry of digital type.Digitizing final IF signals rather than baseband signals, as done inpreferred embodiments of the invention reduces the number ofanalog-to-digital conversion procedures that must be done and avoids anyproblem with tracking the conversion characteristics of twoanalog-to-digital converters used in the QAM synchrodyning circuitry.

However, in other embodiments of the invention synchrodyning of the QAMsignal to baseband is done using in-phase and quadrature-phase analogsynchronous detectors, which are followed by analog-to-digitalconversion circuitry for digitizing response from the in-phase analogsynchronous detector to generate a real sample stream of interleaved QAMsymbol code and for digitizing response from the quadrature-phase analogsynchronous detector to generate an imaginary sample stream ofinterleaved QAM symbol code.

In other embodiments of the invention, adapted from the DTV receivertype used in field testing during the development of the ATSC standard,synchrodyning of the VSB signal to baseband is done using an analogsynchronous detector, which is followed by an analog-to-digitalconverter (ADC) for digitizing response from the analog synchronousdetector to generate a sample stream of interleaved VSB symbol code andthen bcode and then by a baseband phase tracker. In these otherembodiments of the invention the decimation filter takes its inputsignal directly from the response of the baseband phase tracker.

The preferred embodiments of the invention use digital synchrodyningprocedures to achieve “wrap-around” of symbol phase adjustment. Theadjustment of symbol phase takes place in a bandpass transform of thebaseband, so if the ROMs storing digital carrier are addressed suitably,symbol phase adjustment takes place on a closed cycle of adjustmentrange, rather than on an open linear adjustment range. If there is onlyan open linear adjustment range for symbol phase, which is all that isavailable at baseband, when the limit of adjustment range is reachedsymbol phasing will jump in time displacement. This jump in time willcause repetition of symbols in the symbol coding stream or will causeloss of symbols in the symbol coding stream, depending on whether thejump in time displacement is backward or is forward. These effectsundesirably interfere with symbol counting within the data line in whichthe jump in time displacement occurs, causing temporary loss of datasynchronization.

Television engineers are currently considering using the digitaltransmission system for HDTV for transmitting other types of televisionsignals—for example, four television signals with resolution similar topresent-day NTSC signals that are simultaneously transmitted. Theinvention is suitable for use in receivers for these alternativetransmission schemes, and the claims which follow should be construedbroadly enough to include such receivers within their scope.

In the claims which follow, the word “said” is used whenever referenceis made to an antecedent, and the word “the” is used for grammaticalpurposes other than to refer back to an antecedent.

What is claimed is:
 1. A digital television (DTV) signal receivercomprising: a radio receiver portion for selecting a channel forreception, for converting DTV signal in the selected channel tointermediate frequencies for filtering and amplification, and forsynchrodyning an analog final intermediate-frequency output signalresulting from said filtering and amplification to baseband thereby togenerate a baseband signal; an analog-to-digital converter (ADC)included in said radio receiver portion for sampling one of said signalstherein and digitizing it, so that said baseband signal is supplied fromsaid radio receiver portion as a first stream of digital samplesdescriptive of said baseband signal; a sample clock generator forsupplying a sample clock signal to time the sampling by said ADC so thatsaid first stream of digital samples has a sample rate substantiallyequal to a prescribed multiple MN times the symbol rate of said DTVsignal, MN being the product of a positive number M greater than one andof a positive integer N at least two; an N:1 decimator connected forreceiving said first stream of digital samples and generating inresponse thereto a second stream of digital samples at a sample rate oneN^(th) that of said first stream of digital samples; a channel equalizerfor performing channel equalization on said second stream of digitalsamples to generate a channel equalizer response; and symbol decodingcircuitry for decoding symbols in said channel equalizer response, ascorrected for symbol phase error, to recover groups of bitscorresponding to decoded symbols.
 2. A DTV signal receiver as set forthin claim 1 wherein said sample clock generator comprises: an oscillatorfor supplying oscillations at a frequency controlled by an automaticfrequency and phase control signal; circuitry for generating said sampleclock signal at a rate responsive to said oscillation frequency; an FIRfilter for supplying a bandpass response to said first stream of digitalsamples which bandpass response is centered on a subharmonic of thesymbol rate of said DTV signal; a frequency multiplier for multiplyingthe frequency of a component of said bandpass response at saidsubharmonic of the symbol rate of said DTV signal to generate a harmonicof the symbol rate of said DTV signal; and an automatic frequency andphase control detector for detecting frequency and phase error betweenthe sampling rate of said ADC and said harmonic of the symbol rate ofsaid DTV signal, for application to said oscillator as its saidautomatic frequency and phase control signal.
 3. A DTV signal receiveras set forth in claim 2, wherein N equals
 2. 4. A DTV signal receiver asset forth in claim 2, wherein M equals 1 and N equals
 2. 5. A DTV signalreceiver as set forth in claim 1, wherein N equals
 2. 6. A DTV signalreceiver as set forth in claim 1, wherein M equals 1 and N equals
 2. 7.A DTV signal receiver as set forth in claim 1, further comprising: datasynchronization recovery circuitry for detecting data synchronizationinformation extracted from said second stream of digital samples; ade-interleaver for said bit groups; a Reed-Solomon decoder receiving theresponse of said de-interleaver as its input signal; and a de-randomizerresponsive to the results from said Reed-Solomon decoder for restoring asignal randomized prior to transmission to said DTV receiver.
 8. A DTVsignal receiver as set forth in claim 7, wherein said datasynchronization recovery circuitry is of a type for detecting datasynchronization responsive to groups of bits said symbol decoder decodesfrom symbols in said channel equalizer.
 9. A DTV signal receiver as setforth in claim 7, wherein said data synchronization recovery circuitryis of a type employing match filters for detecting data synchronizationresponsive to said second stream of digital samples.
 10. A DTV signalreceiver as set forth in claim 9, wherein said data synchronizationrecovery circuitry is connected to receive said second stream of digitalsamples after said channel equalizer has performed channel equalizationthereon.
 11. A DTV signal receiver as set forth in claim 1, wherein saidADC is connected for sampling said analog final intermediate-frequencyoutput signal, and wherein the synchrodyning of said analog finalintermediate-frequency output signal to baseband is done by digitalsynchrodyning apparatus for QAM digital television signals.
 12. A DTVsignal receiver as set forth in claim 11, further comprising: datasynchronization recovery circuitry for detecting data synchronizationresponsive to groups of bits said symbol decoder decodes from symbols insaid channel equalizer response; a de-interleaver for said bit groups; aReed-Solomon decoder receiving the response of said de-interleaver asits input signal; and a de-randomizer responsive to the results fromsaid Reed-Solomon decoder for restoring a signal randomized prior totransmission to said DTV receiver.
 13. A DTV signal receiver as setforth in claim 11, further comprising: data synchronization recoverycircuitry employing match filters for detecting data synchronizationresponsive to said second stream of digital samples; a de-interleaverfor said bit groups; a Reed-Solomon decoder receiving the response ofsaid de-interleaver as its input signal; and a de-randomizer responsiveto the results from said Reed-Solomon decoder for restoring a signalrandomized prior to transmission to said DTV receiver.
 14. A DTV signalreceiver as set forth in claim 13, wherein said data synchronizationrecovery circuitry is connected to receive said second stream of digitalsamples after said channel equalizer has performed channel equalizationthereon.
 15. A DTV signal receiver as set forth in claim 11, whereinsaid sample clock generator comprises: an oscillator for supplyingoscillations at a frequency controlled by an automatic frequency andphase control signal; circuitry for generating said sample clock signalat a rate responsive to said oscillation frequency; an FIR filter forsupplying a bandpass response to said first stream of digital sampleswhich bandpass response is centered on a subharmonic of the symbol rateof said DTV signal; a frequency multiplier for multiplying the frequencyof a component of said bandpass response at said subharmonic of thesymbol rate of said DTV signal to generate a harmonic of the symbol rateof said DTV signal; and an automatic frequency and phase controldetector for detecting frequency and phase error between the samplingrate of said ADC and said harmonic of the symbol rate of said DTVsignal, for application to said oscillator as its said automaticfrequency and phase control signal.
 16. A DTV signal receiver as setforth in claim 15, further comprising: data synchronization recoverycircuitry for detecting data synchronization responsive to groups ofbits said symbol decoder decodes from symbols in said channel equalizerresponse; a de-interleaver for said bit groups; a Reed-Solomon decoderreceiving the response of said de-interleaver as its input signal; and ade-randomizer responsive to the results from said Reed-Solomon decoderfor restoring a signal randomized prior to transmission to said DTVreceiver.
 17. A DTV signal receiver as set forth in claim 15, furthercomprising: data synchronization recovery circuitry employing matchfilters for detecting data synchronization responsive to said secondstream of digital samples; a de-interleaver for said bit groups; aReed-Solomon decoder receiving the response of said de-interleaver asits input signal; and a de-randomizer responsive to the results fromsaid Reed-Solomon decoder for restoring a signal randomized prior totransmission to said DTV receiver.
 18. A DTV signal receiver as setforth in claim 17, wherein said data synchronization recovery circuitryis connected to receive said second stream of digital samples after saidchannel equalizer has performed channel equalization thereon.
 19. A DTVsignal receiver as set forth in claim 1, wherein said ADC is connectedfor sampling said analog final intermediate-frequency output signal, andwherein the synchrodyning of said analog final intermediate-frequencyoutput signal to baseband is done by digital synchrodyning apparatus forVSB digital television signals.
 20. A DTV signal receiver as set forthin claim 19, further comprising: data synchronization recovery circuitryfor detecting data synchronization responsive to groups of bits saidsymbol decoder decodes from symbols in said channel equalizer response;a de-interleaver for said bit groups; a Reed-Solomon decoder receivingthe response of said de-interleaver as its input signal; and ade-randomizer responsive to the results from said Reed-Solomon decoderfor restoring a signal randomized prior to transmission to said DTVreceiver.
 21. A DTV signal receiver as set forth in claim 19, furthercomprising: data synchronization recovery circuitry employing matchfilters for detecting data synchronization responsive to said secondstream of digital samples; a de-interleaver for said bit groups; aReed-Solomon decoder receiving the response of said de-interleaver asits input signal; and a de-randomizer responsive to the results fromsaid Reed-Solomon decoder for restoring a signal randomized prior totransmission to said DTV receiver.
 22. A DTV signal receiver as setforth in claim 21, wherein said data synchronization recovery circuitryis connected to receive said second stream of digital samples after saidchannel equalizer has performed channel equalization thereon.
 23. A DTVsignal receiver as set forth in claim 19, wherein said sample clockgenerator comprises: an oscillator for supplying oscillations at afrequency controlled by an automatic frequency and phase control signal;circuitry for generating said sample clock signal at a rate responsiveto said oscillation frequency; an FIR filter for supplying a band passresponse to said first stream of digital samples which bandpass responseis centered on a subharmonic of the symbol rate of said DTV signal; afrequency multiplier for multiplying the frequency of a component ofsaid bandpass response at said subharmonic of the symbol rate of saidDTV signal to generate a harmonic of the symbol rate of said DTV signal;and an automatic frequency and phase control detector for detectingfrequency and phase error between the sampling rate of said ADC and saidharmonic of the symbol rate of said DTV signal, for application to saidoscillator as its said automatic frequency and phase control signal. 24.A DTV signal receiver as set forth in claim 23, further comprising: datasynchronization recovery circuitry for detecting data synchronizationresponsive to groups of bits said symbol decoder decodes from symbols insaid channel equalizer response; a de-interleaver for said bit groups; aReed-Solomon decoder receiving the response of said de-interleaver asits input signal; and a de-randomizer responsive to the results fromsaid Reed-Solomon decoder for restoring a signal randomized prior totransmission to said DTV receiver.
 25. A DTV signal receiver as setforth in claim 23, further comprising: data synchronization recoverycircuitry employing match filters for detecting data synchronizationresponsive to said second stream of digital samples; a de-interleaverfor said bit groups; a Reed-Solomon decoder receiving the response ofsaid de-interleaver as its input signal; and a de-randomizer responsiveto the results from said Reed-Solomon decoder for restoring a signalrandomized prior to transmission to said DTV receiver.
 26. A DTV signalreceiver as set forth in claim 25, wherein said data synchronizationrecovery circuitry is connected to receive said second stream of digitalsamples after said channel equalizer has performed channel equalizationthereon.
 27. A DTV signal receiver for recovering baseband digitalsamples of symbol code from the DTV signal, including ananalog-to-digital converter for sampling the DTV signal in accordancewith a first sample clock signal and a a sample clock generator forgenerating said first sample clock signal, said sample clock generatorcomprising: a controlled oscillator for supplying oscillations;circuitry for supplying said first sample clock signal as timed by saidoscillations; a narrow bandpass, finite-impulse-response (FIR), firstdigital filter centered at a frequency that is a subharmonic of thesymbol rate of said symbol code having substantial strength, said firstdigital filter connected for supplying a first digital filter responseto said baseband digital samples of symbol code, which said firstdigital filter response contains said subharmonic of the symbol rate ofsaid symbol code; a frequency multiplier for supplying, in response tosaid first digital filter response, a frequency multiplier response thatcontains a multiple of said subharmonic of the symbol rate of saidsymbol code; and automatic-frequency-and-phase-control circuitryresponsive to said multiple of said subharmonic of the symbol rate ofsaid symbol code in said frequency multiplier response and to a signalderived from the oscillations of said controlled oscillator fordeveloping an automatic-frequency-and-phase-control (AFPC) signal forsaid controlled oscillator.
 28. A DTV signal receiver as set forth inclaim 27, wherein said controlled oscillator is of a type supplyingcissoidal oscillations at a frequency twice symbol frequency, andwherein said circuitry for supplying said first sample clock signal astimed by said oscillations comprises: clipper circuitry forsymmetrically clipping said cissoidal oscillations to generateessentially square waves of said frequency twice symbol frequency, usedas said first sample clock signal.
 29. A DTV signal receiver as setforth in claim 28, wherein said sample clock generator furthercomprises: a flip-flop connected as a frequency divider for respondingto said essentially square waves of said frequency twice symbolfrequency to generate square waves of said symbol frequency, said signalderived from the oscillations of said controlled oscillator that saidautomatic-frequency-and-phase-control circuitry is responsivecorresponding to said square waves of said symbol frequency.
 30. A DTVsignal receiver as set forth in claim 29, further comprising: a 2:1decimator responsive to said baseband digital samples of symbol codefrom the DTV signal for supplying an output signal with half as manysamples therein; a channel equalization filter responsive to the outputsignal from said 2:1 decimator; and an AND gate included in said sampleclock generator for generating an AND response to said essentiallysquare waves of said frequency twice symbol frequency from said clippercircuitry and to said square waves of said symbol frequency from saidflip-flop, said AND response being supplied as a second sample clockfrequency to said 2:1 decimator for timing the samples in the outputsignal from said 2:1 decimator.
 31. A DTV signal receiver as set forthin claim 30, wherein said frequency multiplier comprises: a firstsquaring circuit for squaring said first digital filter response todevelop a squared first digital filter response containing secondharmonics of the components of said first digital filter response; and anarrow bandpass, finite-impulse-response (FIR), second digital filtercentered at a frequency that corresponds to the symbol rate of saidsymbol code, said second digital filter connected for filtering saidsquared first digital filter response for supplying a second digitalfilter response.
 32. A DTV signal receiver as set forth in claim 31,wherein said second digital filter response is applied to saidautomatic-frequency-and-phase-control circuitry as said multiple of saidsubharmonic of the symbol rate of said symbol code in said frequencymultiplier response.
 33. A DTV signal receiver as set forth in claim 31,wherein said frequency multiplier further comprises: a second squaringcircuit for squaring said second digital filter response to develop asquared second digital filter response containing second harmonics ofthe components of said second digital filter response; and a narrowbandpass, finite-impulse-response (FIR), third digital filter centeredat a frequency that corresponds to twice the symbol rate of said symbolcode, said third digital filter connected for filtering said squaredsecond digital filter response for supplying a third digital filterresponse applied to said automatic-frequency-and-phase-control circuitryas said multiple of said subharmonic of the symbol rate of said symbolcode in said frequency multiplier response.
 34. A DTV signal receiver asset forth in claim 27, wherein said frequency multiplier comprises: afirst squaring circuit for squaring said first digital filter responseto develop a squared first digital filter response containing secondharmonics of the components of said first digital filter response; and anarrow bandpass, finite-impulse-response (FIR), second digital filtercentered at a frequency that corresponds to the symbol rate of saidsymbol code, said second digital filter connected for filtering saidsquared first digital filter response for supplying a second digitalfilter response.
 35. A DTV signal receiver as set forth in claim 34,wherein said second digital filter response is applied to saidautomatic-frequency-and-phase-control circuitry as said multiple of saidsubharmonic of the symbol rate of said symbol code in said frequencymultiplier response.
 36. A DTV signal receiver as set forth in claim 34,wherein said frequency multiplier further comprises: a second squaringcircuit for squaring said second digital filter response to develop asquared second digital filter response containing second harmonics ofthe components of said second digital filter response; and a narrowbandpass, finite-impulse-response (FIR), third digital filter centeredat a frequency that corresponds to twice the symbol rate of said symbolcode, said third digital filter connected for filtering said squaredsecond digital filter response for supplying a third digital filterresponse applied to said automatic-frequency-and-phase-control circuitryas said multiple of said subharmonic of the symbol rate of said symbolcode in said frequency multiplier response.
 37. A digital television(DTV) signal receiver for receiving a plurality of DTV signal formatshaving different symbol rates, comprising: a radio receiver portion forselecting a channel for reception and generating a baseband signal ofsaid selected channel; an analog-to-digital converter (ADC) included insaid radio receiver portion for sampling one of said signals therein anddigitizing it, so that said baseband signal is supplied from said radioreceiver portion as a first stream of digital samples descriptive ofsaid baseband signal; a sample clock generator for supplying a sampleclock signal to time the sampling by said ADC so that said first streamof digital samples has a predetermined sample rate which is greater thanthe symbol rate of the received DTV signal; a decimator connected forreceiving said first stream of digital samples and generating inresponse thereto a second stream of digital samples, wherein the rate ofgeneration of said second stream of digital samples is substantiallyequal to said symbol rate of said received DTV signal when its format isof a first type and wherein said rate of generations of said secondstream of digital samples is a multiple of said symbol rate of saidreceived DTV signal when its format is of a second type; a channelequalizer for performing channel equalization on said second stream ofdigital samples to generate a channel equalizer response; and symboldecoding circuitry for decoding symbols in said channel equalizerresponse, as corrected for symbol phase error, to recover groups of bitscorresponding to decoded symbols.
 38. A DTV signal receiver as claimedin claim 37, wherein said first type of DTV signal format is the VSBtype and said second type of DTV signal format is the QAM type.
 39. ADTV signal receiver as claimed in claim 37, wherein a single channelequalizer generates said channel equalizer response in accordance withthe type of said DTV signal format received.
 40. A DTV signal receiveras set forth in claim 1, further comprising: a sample clock generatorfor supplying a sample clock signal to time the sampling by said ADC sothat said first stream of digital samples has a sample ratesubstantially equal to a prescribed multiple MN times the symbol rate ofsaid DTV signal, MN being the product of a positive number M greaterthan one and of a positive integer N at least two.
 41. A DTV signalreceiver as claimed in 37, wherein the rate of generation of said secondstream of digital samples is an integer multiple of said symbol rate.42. A digital television (DTV) signal receiver for receiving a pluralityof DTV signal formats having different symbol rates, comprising: a radioreceiver portion for selecting a channel for reception and generating abaseband signal of said selected channel; an analog-to-digital converter(ADC) included in said radio receiver portion for sampling one of saidsignals therein and digitizing it, so that said baseband signal issupplied from said radio receiver portion as a first stream of digitalsamples descriptive of said baseband signal; a sample clock generatorfor supplying a sample clock signal to time the sampling by said ADC sothat said first stream of digital samples has a predetermined samplerate which is greater than the symbol rate of the received DTV signal; adecimator connected for receiving said first stream of digital samplesand generating in response thereto a second stream of digital samples,wherein the rate of generation of said second stream digital samples issubstantially equal to said symbol rate of said receiver DTV signal whenits format is of a first type and wherein the rate generation of saidsecond stream of digital samples is equal to said symbol rate multipliedby a factor other than an integer when the format of said received DTVsignal is of a second type; a channel equalizer for performing channelequalization on said second stream of digital samples to generate achannel equalizer response; and symbol decoding circuitry for decodingsymbols in said channel equalizer response, as corrected for symbolphase error, to recover groups of bits corresponding to decoded symbols.43. A digital television (DTV) signal receiver for receiving a pluralityof DTV signal formats having different symbol rates, comprising: a radioreceiver portion for selecting a channel for reception and generating abaseband signal of said selected channel; an analog-to-digital converter(ADC) included in said radio receiver portion for sampling one of saidsignals therein and digitizing it, so that said baseband signal issupplied from said radio receiver portion as a first stream of digitalsamples descriptive of said baseband signal; a signal clock generatorfor supplying a sample clock signal to time the sampling by said ADC sothat said first stream of digital samples has a predetermined samplerate which is greater than the symbol rate of the received DTV signal; adecimator connected for receiving said first stream of digital samplesand generating in response thereto a second stream of digital samples,wherein the rate of generation of said second stream of digital samplesis substantially equal to said symbol rate of said received DTV signalwhen its format is of a first type and wherein said rate of generationof said second stream of digital sample is higher than said symbol rateof said received DTV signal when its format is of a second type; achannel equalizer for performing channel equalization on said secondstream of digital samples to generate a channel equalizer response; andsymbol decoding circuitry for decoding symbols in said channel equalizerresponse, as corrected for symbol phase error, to recover groups of bitscorresponding to decoded symbols.
 44. A digital television (DTV) signalreceiver for receiving a plurality of DTV signal formats havingdifferent symbol rates, comprising: a radio receiver portion forselecting a channel for reception and generating a baseband signal ofsaid selected channel; an analog-to-digital converter (ADC) included insaid radio receiver portion for sampling one of said signals therein anddigitizing it, so that said baseband signal is supplied from said radioreceiver portion as a first stream of digital samples descriptive ofsaid baseband signal; a sample clock generator for supplying a sampleclock signal to time the sampling by said ADC so that said first streamof digital samples has a predetermined sample rate which is greater thanboth a first symbol rate of the received DTV signal when its format isof a first type and a second symbol rate of the received DTV signal whenits format is of a second type; a decimator connected for receiving saidfirst stream of digital samples and generating in response thereto asecond stream of digital samples, wherein the rate of generation of saidsecond stream of digital samples is substantially equal to a multiple ofboth said first and second symbol rates; a channel equalizer forperforming channel equalization on said second stream of digital samplesto generate a channel equalizer response; first symbol decodingcircuitry, operative when the format of said received DTV signal is ofsaid first type, for decoding symbols in said channel equalizer responseto recover groups of bits corresponding to decoded symbols as a firstsymbol decoding circuitry response; and second symbol decodingcircuitry, operative when the format of said received DTV signal is ofsaid second type, for decoding symbols in said channel equalizerresponse to recover groups of bits corresponding to decoded symbols as asecond symbol decoding circuitry response.
 45. A DTV signal receiver asclaimed in claim 44, wherein the rate of generation of said secondstream of digital samples is substantially equal to the symbol rate ofthe received DTV signal when its format is of said first type and is ahigher multiple of the symbol rate of the received DTV signal when itsformat is of said second type.
 46. A DTV signal receiver as claimed inclaim 44, wherein said channel equalizer has adjustable weightingcoefficients, which are adjusted by decision-directed equalizationresponsive to said first symbol decoding circuitry response when theformat of said received DTV signals is of said first type, and which areadjusted by decision-directed equalization responsive to said secondsymbol decoding circuitry response when the format of said received DTVsignal is of said second type.